VLSI Engineering
Certificate Program

VLSI Engineering

Building the hardware of tomorrow

Enroll in Certificate View Individual Courses

Certificate Description

Integrated circuit curriculum

Silicon Valley professionals explore ASIC, semiconductor, EDA, device, and integrated circuits in this program. You can pursue five tracks of study:

  • Design Methodology
  • Logic and Functional Design
  • SystemVerilog and Verification
  • Physical Design and Timing Closure
  • Circuit Design

Learn hardware specification, logic design, verification, synthesis, physical implementation, circuit design, integrated circuit product testing, and the latest EDA tools on Linux in our VLSI Lab.

VLSI Engineering certificate program objectives

  • Implement Verilog modeling of digital logic
  • Write assertions for formal verification using SystemVerilog
  • Build an advanced UVM verification environment
  • Understand IO technologies such as PCI Express, Ethernet and Fibre Channel
  • Complete practical designs with Xilinx FPGAs

Cost: $5,800
Required Credits: Total Required: 5–7 courses/14 units. Take 2 of the 5 core courses (6 units) and 3–5 elective credit courses (8–9 units). End with certificate of completion review.
Duration: A full-time student can complete the certificate in 9–12 months.

Courses

Course Units Fall Winter Spring Summer
1. CORE COURSES
Advanced Verification with SystemVerilog OOP Testbench 3.0
Analog IC Design, Introduction 3.0
Digital Logic Design Using Verilog 3.0
Physical Design Flow From Netlist to GDSII 3.0
Practical DFT Concepts for ASICs: Nanometer Test Enhancements 3.0
2. ELECTIVE COURSES: DESIGN METHODOLOGY
Developing the Nanometer ASIC: From Spec to Silicon 2.0
Practical Design with Xilinx FPGAs 3.0
3. ELECTIVE COURSES: LOGIC & FUNCTIONAL DESIGN
Digital Design with FPGA 3.0
Digital Logic Design Using Verilog 3.0
IO Concepts and Protocols: PCI Express, Ethernet, and Fibre Channel 3.0
Practical DFT Concepts for ASICs: Nanometer Test Enhancements 3.0
4. Elective Courses: SystemVerilog & Verification
Advanced Verification with SystemVerilog OOP Testbench 3.0
System and Functional Verification Using UVM (Universal Verification Methodology) 3.0
SystemVerilog Assertions and Formal Verification 3.0
SystemVerilog Essentials: Functional Verification and Simulation 1.5
5. ELECTIVE COURSES: PHYSICAL DESIGN & TIMING CLOSURE
ASIC Physical Design, Advanced 3.0
Physical Design Flow From Netlist to GDSII 3.0
Timing Closure in IC Design 3.0
6. ELECTIVE COURSES: CIRCUIT DESIGN
Analog IC Design, Introduction 3.0
Comprehensive Signal and Power Integrity for High-Speed Digital Systems 3.0
IO Design Fundamentals 3.0
Jitter Essentials 1.5
Wireless Communications and Mobile Antenna Design, Introduction 3.0
7. ELECTIVE COURSES: RELATED ELECTIVES
Embedded System Hardware Architectures, Introduction 3.0
8. REQUIRED CERTIFICATE REVIEW
VLSI Engineering Certificate Completion Fee None

Requisite Knowledge

Technical expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Please review course descriptions

Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Program Chair

Ben Ting, chair

Certificate Program Chair

BENJAMIN TING, M.S.E.E., is a principal engineer at Micron Technology. He is responsible for developing block-to-SOC UVM methodology, architecting Coverage-Driven Verification solutions, and developing re-usable plug-and-play verification components. Prior to joining Micron, Ting was an applications consultant at Synopsys, specializing in design verification using SystemVerilog and Universal Verification Methodology (UVM). He has over 20 years’ experience in the semiconductor and electronic design automation (EDA) industries, including technical and/or leadership roles at Xilinx, AMD, and Cadence Design Systems. His experience encompasses multi-gigabit networking designs, graphics and processors, as well as FPGAs and mixed-signal programmable SOCs. He has experience with chip design for a range of real-world applications, including networking, graphics, processors and FPGAs. Ben has taught at UCSC Extension since 2008.

Certificate Program Advisory Committee

JEFFERY GOODING, MSEE
Account Technology Executive, Cadence Design Systems

SAM HUYNH, Ph.D., MSEE
Principal Member of Technical Staff, AMD
Instructor, VLSI Certificate Program, UCSC Silicon Valley Extension

MANDAR MUNISHWAR, B.E.
Formal Verification Engineer, Google
Instructor, VLSI Certificate Program, UCSC Silicon Valley Extension

JOSE RENAU, Ph.D.
Professor, Computer Science and Engineering, Jack Baskin School of Engineering, UC Santa Cruz
Consultant, Esperanto Technologies, Inc.

BENJAMIN TING, M.S.E.E.
Principal Engineer, Micron Technology
Chair/Instructor, VLSI Certificate Program, UCSC Silicon Valley Extension

MAYEN UDOETUK, Ed.D., MA
Director of Engineering and Technology, Academic Services, UCSC Silicon Valley Extension

Certificate Inquiry Form

Contact Us
Speak to a student services representative.

Call (408) 861-3860

Envelope extension@ucsc.edu

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