5613013

This Program is Perfect For

  • Hardware design and verification engineers aiming to specialize in VLSI and ASIC development
  • Professionals seeking depth in either front-end logic or back-end physical design
  • Working professionals and international students needing structured, flexible credentialing
  • Engineers and technologists preparing to meet the growing global semiconductor workforce demand

Program review underway

Important update for 2026-27

As we evolve our programs to reflect today’s technology landscape, the certificate in Silicon Chip Design & Semiconductor Engineering is under review and is not currently open for new enrollment. If you are enrolled in this certificate and are finishing up your courses, please reach out to us at extension@ucsc.edu. We will help you plan your journey. 

After reviewing the current market conditions and engaging with industry, we are now offering new short programs, that are flexible paths to get the skills you need fast. During this time, our certificate programs continue to be under review and we are committed to assisting all enrolled students to finish the certificate programs. To learn more, visit our Short Programs page.

Courses are open to everyone

You are invited to enroll in individual courses to build your knowledge and develop new skills.

 

Learn next-level VLSI design skills for top Silicon Valley companies

UCSC Silicon Valley Extension Silicon Chip Design & Semiconductor Engineering professional certificate program provides students with the core design skills they need to work at top companies in the Valley. Both established and aspiring engineers develop new skills, gain insight into digital and analog design techniques and methodologies, and learn from our expert faculty.

Integrated circuit curriculum

You'll explore ASIC, semiconductor, EDA, device, and integrated circuits. In our VLSI lab, our instructors will give you the opportunity to get hands-on experience with hardware specification, logic design, verification, synthesis, physical implementation, circuit design, integrated circuit product testing, and the latest EDA tools on Linux.

Two tailored elective tracks

  • Track 1: Front-end Design
    For professionals pursuing careers in application-specific integrated circuits (ASIC) architectural definitions and logic designs for its implementation.
  • Track 2: Back-end Design
    For professionals interested in the physical implementations of ASIC designs from synthesis to silicon.

Certificate program objectives

  • Implement Verilog modeling of digital logic
  • Write assertions for formal verification using SystemVerilog
  • Build an advanced UVM verification environment
  • Understand and implement DFT concepts in an ASIC design
  • Complete practical designs with Xilinx FPGAs
  • Implement a design from RTL to GDS

Access to premier tools

Using premier industry tools from Cadence, OpenROAD, Siemens, and Synopsys, you’ll learn front-end and back-end ASIC design and leave the classroom ready to apply new skills at your job.

synopsys-300.jpg
Cadence_Logo_300px.jpg
siemens-2-300 copy.jpg
openroad-300.jpg

Courses

Program Requirements

Total: 5 courses (minimum 15 quarter units)

  • 3 required courses (9 quarter units)
  • 2 elective courses (minimum 6 quarter units)
  • End with certificate of completion review.

view COURSE Calendar

1. Core Course(s): (Choose Three)
Title units Fall Spring Summer Winter
System and Functional Verification Using UVM (Universal Verification Methodology) 3.0 Live-Online
Practical DFT Concepts for ASICs, SoC and SiP 3.0 Live-Online
AI for Autonomous Driving Systems: Concepts to FPGA 3.0
Advanced Verification with SystemVerilog OOP Testbench 3.0 Live-Online
SystemVerilog Assertions and Formal Verification 3.0 Flexible
2. Electives: Front-End
Title units Fall Spring Summer Winter
High Speed Interface Techniques 3.0 Flexible
Wireless Infrastructure: from Antenna Design to 5G, Fundamentals 3.0 Flexible
Digital Logic Design Using Verilog 3.0 Live-Online
Embedded System Hardware Architectures, Introduction 3.0 Flexible
IO Concepts and Protocols: PCI Express and Ethernet 3.0 Live-Online
Analog IC Design, Introduction 3.0 Live-Online
High-Performance Computer Architecture 3.0 Flexible
3. Electives: Back-End
Title units Fall Spring Summer Winter
High Speed Interface Techniques 3.0 Flexible
3D IC Packaging and Physical Verification 3.0 Live-Online
Timing Closure in Silicon IC Design 3.0
Introduction to VLSI and ASIC Design 3.0 Live-Online
Physical Design Flow From Netlist to GDSII 3.0 Live-Online
Comprehensive Signal and Power Integrity for High-Speed Digital Systems 3.0 Live-Online
Practical Design with Xilinx FPGAs 3.0 Flexible
Practical Design and Implementation of VLSI Memory Devices 3.0
ASIC Physical Design, Advanced 3.0
4. Completion Review:
Title units Fall Spring Summer Winter
Silicon Chip Design & Semiconductor Engineering Certificate Completion Fee
5. Related Workshops
Title units Fall Spring Summer Winter
Semiconductor Design and Innovation Workshop Series: RISC-V: Understanding Computer Architecture Live-Online
Semiconductor Design and Innovation Workshop Series: High-Precision GHz Op Amp Design
Semiconductor Design and Innovation Workshop Series: Timing Constraint Management for Modern System On Chip

1. Core Course(s): (Choose Three)

System and Functional Verification Using UVM (Universal Verification Methodology)
VLSI.X410
$990
You may enroll in this offering at any time.
Keshav Kannan
Keshav Kannan
Sep. 24 - Dec. 3, Thu, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X410.(37)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 09-24-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-01-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-08-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-15-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-22-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-29-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 11-05-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 11-12-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 11-19-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 12-03-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on November 26, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Recommended Text:
The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology, Ray Salemi, Boston Light Press, 2013. ISBN-13: 978-0974164939

A Practical Guide to Adopting the Universal Verification Methodology (UVM), Sharon Rosenberg and Kathleen Meade, Cadence Design Systems, 2010. ISBN: 9780578059556

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X400: Advanced Verification with SystemVerilog OOP Testbench
Fall
Practical DFT Concepts for ASICs, SoC and SiP
VLSI.X409
$990
You may enroll in this offering at any time.
Rajesh Y Pendurkar
Rajesh Pendurkar
Sep. 14 - Nov. 16, Mon, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X409.(17)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 09-14-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 09-21-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 09-28-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-05-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-12-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-19-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-26-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-02-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-09-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-16-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:
VLSI Test Principles & Architectures: Design for Testability, Laung-Terng Wang, et al., Morgan Kaufmann, 2006, ISBN-10: 0123705975, ISBN-13: 978-0123705976.

Recommended Tools & Materials:
Digital Systems Testing and Testable Design; Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman; Wiley-IEEE Press ; 1994-09-27. ISBN: 9780780310629 
Important Note: If you have a previous edition of this book, you do not need to repurchase a more current version for this course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A working knowledge of digital logic design is recommended. 
Fall
AI for Autonomous Driving Systems: Concepts to FPGA
VLSI.X416
$990
You may enroll in this offering at any time.
Sep. 3 - Nov. 5, Thu, 6:00pm - 9:00pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X416.(6)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 09-03-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 09-10-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 09-17-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 09-24-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 10-01-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 10-08-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 10-15-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 10-22-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 10-29-2026 6:00pm 9:00pm Live-Online REMOTE
Thu, 11-05-2026 6:00pm 9:00pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Textbook and Materials:
Fundamentals of Digital Logic with Verilog Design 3rd Ed, Stephen Brown, Zvonko Vranesic, McGraw-Hill Higher Education

For this course, students will need to purchase a board ($100-$150). Details to be discussed in class.

Recommended Tools & Materials:

8 Mega Pixel Digital Cameria Package with GPIO interface from "terasic"."  https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&Cat…

Students can purchase this camera in addition to the FPGA board. ($120 - $150)

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X404: Digital Logic Design Using Verilog

Skills Needed:

  • Some programming knowledge (Python, MATLAB, VHDL, Verilog, SystemVerilog) and digital system design experience is preferred, but not required.
Advanced Verification with SystemVerilog OOP Testbench
VLSI.X400
$990
You may enroll in this offering at any time.
Benjamin Ting
Benjamin Ting
Aug. 25 - Nov. 3, Tue, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X400.(28)
Schedule
Date Start Time End Time Meeting Type Location
Tue, 08-25-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 09-01-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 09-08-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 09-15-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 09-22-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 09-29-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 10-06-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 10-13-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 10-20-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 10-27-2026 6:30pm 9:30pm Live-Online REMOTE
Tue, 11-03-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

One “No meeting” date TBA.  To see all meeting dates, click “Full Schedule” below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
 

Required Texts: (Click on links to order)

"OOP Testbench Workbook"

"Advanced Verification using SystemVerilog OOP Testbench" 


Note: Both books listed above are required for the course. These books are study guides that contain extensive course notes and step-by-step methodology development practices. Shipment by publisher may take 1-2 weeks.

Short descriptions of weekly homework and partial source code will be distributed in class at no additional expense to enrolled students.

The course is graded by Final Project only - homework assignments are not part of the final grade.

Fall
SystemVerilog Assertions and Formal Verification
VLSI.X411
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer

2. Electives: Front-End

High Speed Interface Techniques
VLSI.X405
$595
You may enroll in this offering at any time.
Edison Fong
Edison Fong
Jan. 21 - Mar. 25, Thu, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X405.(19)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 01-21-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 01-28-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-04-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-11-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-18-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-25-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-04-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-11-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-18-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-25-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

Electronic Course Materials: You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A basic course in circuit design and understanding of basic electromagnetic physics.
Fall
Wireless Infrastructure: from Antenna Design to 5G, Fundamentals
EMBD.X419
$495
You may enroll in this offering at any time.
Edison Fong
Edison Fong
Sep. 24 - Dec. 3, Thu, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
EMBD.X419.(13)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 09-24-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 10-01-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 10-08-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 10-15-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 10-22-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 10-29-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 11-05-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 11-12-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 11-19-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 12-03-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

No meeting on November 26, 2026.  To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Recommended Texts: 
The Design of CMOS Radio-Frequency Integrated Circuits; Thomas H. Lee; Cambridge University Press, 2004. ISBN: 9780521835398 

Electronic Communication; Robert L. Shrader; McGraw-Hill Science, 1991. 

The ARRL Handbook for Radio Amateurs 2000; American Radio Relay League; ARRL, 1999. ISBN: 9780872591837

||

Prerequisites / Skills Needed

Skills Needed:

  • A general background in electrical engineering and networking.
Fall
Digital Logic Design Using Verilog
VLSI.X404
$980
You may enroll in this offering at any time.
Parag Bhatt
Parag Bhatt
Sep. 23 - Dec. 9, Wed, 6:00pm - 9:00pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X404.(19)
Schedule
Date Start Time End Time Meeting Type Location
Wed, 09-23-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 09-30-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 10-07-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 10-14-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 10-21-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 10-28-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 11-04-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 11-18-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 12-02-2026 6:00pm 9:00pm Live-Online REMOTE
Wed, 12-09-2026 6:00pm 9:00pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on November 11, 2026 and November 25, 2026.  To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tool: Verilog Simulator, and Synthesis tools.  
Please see Modules in Canvas on how to access the tools.  

||

Prerequisites / Skills Needed

Skills Needed:

  • Knowledge of basic logic design and familiarity with a high-level programming language (e.g., C) and use of a text editor.
Fall
Embedded System Hardware Architectures, Introduction
EMBD.X415
$820
You may enroll in this offering at any time.
Michael A. Wang
Michael Wang
Sep. 14 - Nov. 16, Mon, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
EMBD.X415.(18)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 09-14-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 09-21-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 09-28-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-05-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-12-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-19-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-26-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 11-02-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 11-09-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 11-16-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: None

Recommended Tools & Materials:
Embedded Systems Architecture: A Comprehensive Guide for Engineers and Programmers, 2nd Edition, Noergaard, Tammy, Newnes, 2012, ISBN: 978-0123821966.

||

Prerequisites / Skills Needed

Skills Needed:

  • Some familiarity with the hardware components of a computer system is required.
Fall
IO Concepts and Protocols: PCI Express and Ethernet
EMBD.X406
$950
You may enroll in this offering at any time.
Ajit A Natarajan
Ajit Natarajan
Sep. 2 - Nov. 18, Wed, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
EMBD.X406.(16)
Schedule
Date Start Time End Time Meeting Type Location
Wed, 09-02-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-09-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-16-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-23-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-30-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-07-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-14-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-21-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-28-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 11-04-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 11-18-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on November 11, 2026.  1 "No meeting" date TBA.  To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Recommended Texts:    
PCI-SIG Standards, PCI-SIG (PCI Express). By special arrangement with the PCI-SIG, students will get access to pertinent standards for academic use.     

IEEE 802.3 Standards, IEEE (Ethernet)

 

||

Prerequisites / Skills Needed

Skills Needed:

  • An introductory course or practical experience with operating systems internals, an introduction to computer architecture and organization, and systems programming experience.
Fall
Analog IC Design, Introduction
VLSI.X401
$880 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring
High-Performance Computer Architecture
VLSI.X415
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter

3. Electives: Back-End

High Speed Interface Techniques
VLSI.X405
$595
You may enroll in this offering at any time.
Edison Fong
Edison Fong
Jan. 21 - Mar. 25, Thu, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X405.(19)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 01-21-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 01-28-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-04-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-11-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-18-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 02-25-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-04-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-11-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-18-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Thu, 03-25-2027 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

Electronic Course Materials: You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A basic course in circuit design and understanding of basic electromagnetic physics.
Fall
3D IC Packaging and Physical Verification
VLSI.X418
$990
You may enroll in this offering at any time.
Minhaz Abedin
Oct. 3 - Dec. 12, Sat, 9:00am - 12:00pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X418.(4)
Schedule
Date Start Time End Time Meeting Type Location
Sat, 10-03-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 10-10-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 10-17-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 10-24-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 10-31-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 11-07-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 11-14-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 11-21-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 12-05-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 12-12-2026 9:00am 12:00pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on November 28, 2026.  To see all meeting dates, click “Full Schedule” below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

||

Prerequisites / Skills Needed

Skills Needed:

  • Some familiarity with material science principles and a fundamental knowledge of semiconductor manufacturing processes. 
Fall
Timing Closure in Silicon IC Design
VLSI.X414
$990
You may enroll in this offering at any time.
Sep. 22 - Dec. 1, Tue, 5:30pm - 8:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X414.(17)
Schedule
Date Start Time End Time Meeting Type Location
Tue, 09-22-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 09-29-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 10-06-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 10-13-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 10-20-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 10-27-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 11-03-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 11-10-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 11-17-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 11-24-2026 5:30pm 8:30pm Live-Online REMOTE
Tue, 12-01-2026 5:30pm 8:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

One “no meeting” date TBA. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:   
Static Timing Analysis for Nanometer Designs: A Practical Approach, Bhasker and Chadha, Springer, 2009, ISBN-13: 978-0387938196.

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X403: Introduction to VLSI and ASIC Design
Introduction to VLSI and ASIC Design
VLSI.X403
$990
You may enroll in this offering at any time.
Rajiv Dave, Instructor, Silicon Chip Design & Semiconductor Engineering
Rajiv Dave
Sep. 14 - Nov. 23, Mon, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X403.(13)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 09-14-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 09-21-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 09-28-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-12-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-19-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-26-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-02-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-09-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-16-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-23-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on October 5, 2026. To see all meeting dates, click "Full Schedule" below.

To see all meeting dates, click “Full Schedule” below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:

A Practical Approach to VLSI System on Chip (SoC) Design, Chakravarthi, Veena S., Springer Nature, 2022,  ISBN: 9783031183638.

||

Prerequisites / Skills Needed

Skills Needed:

  • General understanding of digital logic.
  • Lab exercises require some knowledge of Linux.
Fall
Physical Design Flow From Netlist to GDSII
VLSI.X408
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer
Comprehensive Signal and Power Integrity for High-Speed Digital Systems
EMBD.X400
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer
Practical Design with Xilinx FPGAs
EMBD.X408
$910 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer
Practical Design and Implementation of VLSI Memory Devices
VLSI.X417
Currently no classes scheduled. Would you like to be notified when a class is available?
ASIC Physical Design, Advanced
VLSI.X402
Currently no classes scheduled. Would you like to be notified when a class is available?

4. Completion Review:

Silicon Chip Design & Semiconductor Engineering Certificate Completion Fee
O-CE0186
$95
You may enroll in this offering at any time.
Aug. 4, , All Day
O-CE0186.(018)
Schedule
 

Please enroll in the VLSI and Semiconductor Engineering Certificate Completion Fee only when all of the certificate requirements have been met and your final grades are posted.

5. Related Workshops

Semiconductor Design and Innovation Workshop Series: RISC-V: Understanding Computer Architecture
VLSI.800_W2
$95
You may enroll in this offering at any time.
Abhay Singh
Abhay Singh
Dec. 12, Sat, 9:00am - 12:00pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.800_W2.(3)
Schedule
Date Start Time End Time Meeting Type Location
Sat, 12-12-2026 9:00am 12:00pm Live-Online REMOTE
 

This course is part of the Fall 2026 Workshop series.

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Fall
Semiconductor Design and Innovation Workshop Series: High-Precision GHz Op Amp Design
VLSI.800_W3
$95 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Semiconductor Design and Innovation Workshop Series: Timing Constraint Management for Modern System On Chip
VLSI.800_W1
Currently no classes scheduled. Would you like to be notified when a class is available?

Recommended course sequence

Requisite expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Planning your coursework

Beginners should take introductory courses before advanced. Other courses can be taken based on your interests and professional levels.

Please review course descriptions—Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Related electives

  • Embedded System Hardware Architectures, Introduction (3.0)
  • System Design for Low Power Management (1.0)

Substitutions | Shared credits

You may take one elective outside the certificate curriculum if you receive prior approval from the Academic Services Department.

Some technology courses may be listed in more than one program. However, only one course may be shared between two certificate programs unless otherwise noted.

To receive your certificate

Upon completion of the course sequence, you may request your Semiconductor Engineering Certificate Completion Review.

Demo

Establish Candidacy

1. Complete a Course

Complete at least one course in your selected program.

2. Declare Candidacy

Declaring candidacy is free. Click “Enroll” and follow the steps to submit your application online.

3. Complete Requirements

You must establish candidacy in the certificate program before enrolling in the Certificate Completion Review.

Requisite knowledge

Technical expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Please review course descriptions

Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Grade requirements

Please note that only letter grades of C or higher may be applied to a certificate, and in some programs, students may have more stringent requirements. Students in most employer- and government-sponsored payment programs, such as workforce development, as well as international students on F-1 visas, need to maintain a B average to meet their requirements.

See Grading and Credits Policy for further information.

Instructors

Program Chair
Arvind Vidyarthi

Arvind Vidyarthi

Chair | Sr. Dtr., Silicon Design Implementation & Methodology, Altera

ARVIND VIDYARTHI, M.S.E.E. is vice president of Silicon Design Engineering at Altera, where he leads SoC and IP physical design implementation, methodology, and automation. With more than 25 years in the semiconductor industry, he has driven chip implementation across leading companies including Sun Microsystems, AMD, Nvidia, and Intel. His experience spans physical design, timing closure, static timing analysis, floor-planning, and place-and-route. At Intel he led global physical design and data-center AI design implementation, delivering multiple successful tape-outs on advanced process nodes.

A recognized expert across all major implementation tools and methodologies, Vidyarthi is passionate about applying ML/AI to chip design to advance performance, power, and area (PPA) and accelerate turn-around time. 

He holds master's degrees in Electrical Engineering from Tufts University and Binghamton University, and a B.Tech in Electronics Engineering from HBTI.

Beyond his work at Altera, Arvind has served since 2022 as chair of the UCSC Silicon Valley Extension Silicon Chip Design & Semiconductor Engineering program, where he also sits on the VLSI engineering advisory group and mentors the next generation of design engineers.

Abhay Singh
Abhay Singh
Silicon Operations and Partnerships, Google
Ajit A Natarajan
Ajit Natarajan
Sr. Software Engineer, Google
Benjamin Ting
Benjamin Ting
Principal Engineer, Microsoft
Bharat Patel
Bharat Patel
Director/Technologist in the Programmable Solutions Group, Intel
Edison Fong
Edison Fong
RF Engineer and Analog Engineer, Consultant
Emiliano Morini
Emiliano Morini
Principal Formal Verification Engineer, NVIDIA
Ibrahim Delibalta
Ibrahim Delibalta
Sr. Director of SoC Design at Intel Corp.
Jignesh Shah
Jignesh Shah
Principal STA & CAD Engineer, d-Matrix
Joanna Mapel
Joanna Mapel
Field Application Engineer, Xilinx/AMD at Avnet
Keshav Kannan
Keshav Kannan
Verification Lead, Intel Corporation
Lavanya Aryasomayajula
Lavanya Aryasomayajula
Principal Engineer, onsemi
Mandar M Munishwar
Mandar M Munishwar
Formal Verification Architect, Intel Data Center and AI Division
Mehrdad Peyvan
Mehrdad Peyvan
Senior Application Manager, Analog Devices
Michael A. Wang
Michael Wang
Director of Business Development, ISSI Integrated Silicon Solution Inc.
default profile picture
Minhaz Abedin
Parag Bhatt
Parag Bhatt
VP of Engineering, Signature IP Corporation
Rajesh Y Pendurkar
Rajesh Pendurkar
Director of Engineering, Capgemini
Rajiv Dave, Instructor, Silicon Chip Design & Semiconductor Engineering
Rajiv Dave
Senior Product Manager/Principal Engineer
Samit Mehrotra
Samit Mehrotra
Microarchitect, Intel Corp.
Shree Laguduva
Shree Laguduva
ASIC Physical Design Engineer, Apple

Certificate Program Advisory Committee

JEFFERY GOODING, MSEE
Account Technology Executive, Cadence Design Systems

SAM HUYNH, Ph.D., MSEE
Principal Member of Technical Staff, AMD
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JIM SCHULTZ, B.S.
Product Marketing Manager, Digital Design Implementation, Synopsys Inc.

MANDAR MUNISHWAR, B.E.
Formal Verification Architect, Intel Data Center and AI Division
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JOSE RENAU, Ph.D.
Professor, Computer Science and Engineering, Jack Baskin School of Engineering, UC Santa Cruz
Consultant, Esperanto Technologies, Inc.

BENJAMIN TING, M.S.E.E.
Principal Engineer, Micron Technology
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

ARVIND VIDYARTHI, M.S.E.E.
Senior Director, Silicon Design Implementation and Methodology, Altera (an Intel company)|
Program Chair | Instructor, Silicon Chip Design and Semiconductor Engineering

Related Programs

Demo