As manufacturing integrated circuits becomes increasingly complex in the sub nanometer process technology, the timing closure of designs such as ASIC, FPGA, GPU, and SoC becomes more challenging.
In this course you will learn about all stages of physical design including RTL for logic changes and the standard industry practice of performing a static timing analysis (STA) on the design before signing off to manufacturing.
We will begin with the basic timing concepts and a tool agostic STA methodology, introducing you to setup/hold timing. We’ll explain how to fix violations in the design and you will learn what needs to be timed and how to set up and execute STA flow. The course exposes students to constraints, exceptions and what-if analysis. We also explain how to address timing violations in ECO mode.
Advanced technology topics include noise analysis, prevention and on-chip variations. The instructor will share practical experiences meeting timing closure, budgeting, and debugging. Students will explore design tools and practice on test cases. Design engineers completing this course will be able to perform static timing analysis using Primetime, OpenROAD, or any other STA tool in multiple phases of the integrated circuit design process.
At the conclusion of the course, you should be able to:
- Discuss in-depth knowledge of static timing analysis
- Write and debug constraints
- Drive timing closure for block or chip
- Write ECOs
- Explain how to fix critical timing paths
- Define miscellaneous terms such as PVTs, OCV, CRPR, Noise, etc.
Skills Needed: Linux/Unix skills are required for lab exercises.
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