Advanced Verification with SystemVerilog OOP Testbench

SystemVerilog is the new IEEE-1800 standard combining the hardware description language and hardware verification language. This course focuses on the use of advanced verification features in SystemVerilog. Students will learn the step-by-step processes of creating flexible verification components, which form the basis of modern industry-standard methodologies such as UVM (Universal Verification Methodology). They will also gain experience developing an industrial-strength object-oriented programming (OOP) testbench that is layered, configurable, constrained-random, and coverage-driven.

The course starts with a brief review of SystemVerilog language semantics and simulation fundamentals such as event ordering, delta cycles and race conditions, which will then feed into closely related entities in program block, clocking block, and interfaces. Students will learn how to develop a complete verification environment by building flexible testbench components via the use of virtual interfaces, classes, mailboxes, dynamic arrays, and queues, etc. Functional coverage in the form of covergroup, coverpoint, and SystemVerilog Assertion (SVA), will round up the development of a complete verification environment. You will become familiar with the flexibility of an OOP-centric technique, the power of constrained random verification and the use of functional coverage tools to ensure the success of a verification project.

Concepts introduced in class are reinforced in the lab. In addition to in-class hands-on labs and weekly take-home assignments, students will work on a required project to build an advanced OOP testbench and verification environment for a selected application (such as a 10G Ethernet MAC design), with transaction-level and layered architecture. Students will form a project team, create a test plan, develop an OOP-centric verification environment, perform functional coverage, and submit a complete project report. This course builds the foundation for the course "System and Functional Verification Using UVM (Universal Verification Methodology)."

Topics Include:

  • Event scheduler, delta cycles, race conditions, and related topics in program block, clocking block and SystemVerilog interface
  • Virtual interface and classes: deployment of classes in OOP Testbench
  • Stimulus generation technique
  • Constraint inheritance and constraint layering in OOP testbench
  • Functional coverage class as a testbench component
  • Simulation phases

Skills Needed: A course in SystemVerilog and knowledge of VHDL, Verilog, C/C++, and some hardware verification experience. Ability to install and configure open-source software on own computers.


Sections Open for Enrollment:

Open Sections and Schedule
Start / End Date Units Location Cost Instructor
09-15-2020 to 11-17-2020 3.0 ONLINE $1020

Benjamin Ting



Date: Start Time: End Time: Meeting Type: Location:
Tue, 09-15-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 09-22-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 09-29-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 10-06-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 10-13-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 10-20-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 10-27-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 11-03-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 11-10-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE
Tue, 11-17-2020 6:30 p.m. 9:30 p.m. Live-Online ONLINE

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