Course

Comprehensive Signal and Power Integrity for High-Speed Digital Systems


High-speed signaling technologies with multi-gigabit data transfer rates are critical to high-bandwidth communications. However, the physical limitations of the channel (in board, package, and connector), the transceiver circuits, as well as voltage and timing noises introduced along the signal paths, make the design of high-speed links very challenging. Accurate modeling and analysis of high-speed digital systems requires a good understanding of physical effects and system architecture in order to optimize the design parameters in the channel, transmitter, and receiver subsystems. This course gives students a set of skills for problem solving and strategies that they can use to design successful high-speed systems.

This course starts with a comprehensive overview of signal and power integrity analysis for high-speed systems. The instructor promptly moves on to cover the state-of-the art modeling and analysis techniques used in high-speed links. The course introduces accurate interconnect modeling including high frequency and second-order effects, and behavioral modeling of IO and ESD, including IBIS. Students will learn the concepts of equalization design and various signaling techniques (such as differential, NRZ, pulse, multi-level, etc.). At the system level, topics include clocking schemes and timing jitter analysis, as well as power analysis topics such as IR Drop, AC noise, simultaneous switching noise, and decoupling capacitor. The course concludes with a discussion of variations in manufacturing and methods to handle them in simulation and design.

Upon completing the course, students will have a strong understanding of signal and power integrity concepts and terminology. They will acquire the skills to design, model, and analyze high-speed interconnects. They will be able to relate various link blocks and parameters to system performance and make trade off decisions.

Topics include:

  • An introduction to signal and power integrity in high-speed system design
  • Modeling and analysis of passive components
  • I/O driver and receiver modeling
  • Signaling techniques
  • High-speed link statistical simulation methods
  • Equalization
  • Clocking schemes
  • Timing jitter and noise
  • Power supply analysis
  • Modeling and analysis of process and manufacturing variations

  • Skills Needed: Students must have a basic understanding of signal integrity, electromagnetic compatibility, printed circuit boards or packages.

Prerequisite(s):


EMBD.X407

Sections Open for Enrollment:

Open Sections and Schedule
Start / End Date Units Location Cost Instructor
02-14-2020 to 04-24-2020 3.0 CLASSROOM $1020

Wendem Beyene

Enroll

Schedule

Date: Start Time: End Time: Meeting Type: Location:
Fri, 02-14-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 02-28-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 03-06-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 03-13-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 03-20-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 03-27-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 04-03-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 04-10-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 04-17-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Fri, 04-24-2020 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA

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