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Instructor

Benjamin Ting LinkedIn

BENJAMIN TING, M.S.E.E., is a principal engineer at Micron Technology. He is responsible for developing block-to-SOC UVM methodology, architecting Coverage-Driven Verification solutions, and developing re-usable plug-and-play verification components. Prior to joining Micron, Ting was an applications consultant at Synopsys, specializing in design verification using SystemVerilog and Universal Verification Methodology (UVM). He has over 20 years’ experience in the semiconductor and electronic design automation (EDA) industries, including technical and/or leadership roles at Xilinx, AMD, and Cadence Design Systems. His experience encompasses multi-gigabit networking designs, graphics and processors, as well as FPGAs and mixed-signal programmable SOCs. He has experience with chip design for a range of real-world applications, including networking, graphics, processors and FPGAs. Ben has taught at UCSC Extension since 2008.

Benjamin Ting's courses currently open for enrollment

Advanced Verification with SystemVerilog OOP Testbench

Start Date End Date Units Meeting Type Cost
09-16-2021 12-02-2021 3.0 SANTA CLARA / REMOTE $1020.00 Enroll

System and Functional Verification Using UVM (Universal Verification Methodology)

Start Date End Date Units Meeting Type Cost
09-21-2021 11-23-2021 3.0 SANTA CLARA / REMOTE $1020.00 Enroll