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Instructor

Arvind Vidyarthi

Arvind Vidyarthi LinkedIn

"Timing is everything. Too late, or even too early, leads to violations."

Arvind Vidyarthi, MS, Physical Design Lead, Intel

ARVIND VIDYARTHI, M.S.E.E., senior director of silicon design implementation and methodology at Intel, has 17+ years of industry experience in chip implementation in various major semiconductor companies such as Sun Microsystems, AMD, and Nvidia. He has successfully managed chip design tapeouts at Intel and is familiar with all major implementation tools and methodologies. He is passionate about ML/AI in physical design and timing closure for performance, power, and area (PPA) and turn-around-time improvement. He is an instructor and chair of the UCSC Silicon Valley Extension VLSI Engineering certificate program since 2022.

Associated Program(s)
VLSI Engineering