Instructor

Jignesh Shah LinkedIn

"Due to global COVID-19-related shortages, more companies are building their own silicon products and the demand for timing closure skills in digital design is very high. I am super excited to teach the key skills needed for these jobs."

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JIGNESH SHAH, a senior IEEE member, has over two decades of experience in designing CPU, SOC, ASIC, and FPGA products in transistor process technology nodes of 130 um to 5 nm. He is a senior principal physical design engineer at SIMA.ai, an AI/ML accelerator startup. His core expertise is in the areas of defining timing signoff, STA flow automation, clock frequency optimization, and full chip timing closure. Before joining SIMA, Shah worked at Silicon Valley semiconductor companies of all sizes. He is also a past technical chair of TAU, an ACM international workshop on timing issues of digital systems. He has frequently presented on timing analysis methodology and is super excited to teach timing analysis and closure skills at UCSC Silicon Valley Extension.

Associated Program(s)

Silicon Chip Design & Semiconductor Engineering

Semiconductor Design and Innovation Workshop Series: Timing Constraint Management for Modern System On Chip

Timing Closure in Silicon IC Design