This unique course covers each step in developing an ASIC, explaining in an intuitive and visual manner such key concepts as transistor action, standard cells, RTL synthesis, meeting timing, functional coverage, formal equivalence, physical design, signal integrity, DFT and BIST, tape-out, IC fabrication, and emerging packaging trends.
Through hands-on quick tour labs students become familiar with the roles of synthesis, simulation, formal equivalence, and routing tools. The focus is on mostly-digital ASICs with multiple IP cores, low-power goals, and on-chip analog blocks. A preview of the latest technology, including nanosheets and gate-all-around transistors.
The course is intended for ASIC professionals, both experienced and entry-level who are seeking a more in-depth understanding of the chip development flow. Knowledge gained in this course will improve cross-functional communication with other team members and prepare students for more rigorous study in the ASIC or SoC field.
At the conclusion of the course, you should be able to
- Describe the overall design and verification flows for ASICs and FPGAs and identify the EDA tools used at each major stage.
- Bring hardware engineers up to speed on the latest ASIC technology and methodology.
- Respond appropriately to challenging VLSI ASIC and FPGA interview questions.
- Describe the increasingly complex ASIC development flow.
- Overview of ASIC architectures
- Integration of IP cores: formats, deliverables, and watermarks
- Overcome the verification bottleneck: embedded assertions, constrained random tests, equivalence checking and emulation
- How on-chip firmware code interacts with the chip’s hardware
- Create layout for tape-out: metal layers and vias, routing insights, noise avoidance, DFM issues, timing closure
- Business practices with silicon foundries: sort, shuttles, corner lots
- Comprehensive coverage of the chip design flow, from spec through tape-out to fabrication and packaging, equipping students for follow-on courses in RTL design, verification, DFT, and layout
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