Physical Design Flow From Netlist to GDSII

With shrinking process technologies, physical design is becoming extremely challenging. Physical designers are responsible for producing high quality design tapeout, and an understanding of all aspects of physical design from synthesis to tapeout is critical to success. This course is an introduction to the ASIC physical design flow and tools from netlist (gate level) to GDS-II (fractured data).

After an overview of the ASIC physical design flow and synthesis, the course starts with floor planning and block pin assignment. It then covers placement and clock-tree synthesis, followed by routing, and post-route optimization. You will learn RC extraction, static timing analysis, and physical verification. Upon completion of this course, you will possess the essential knowledge and hands-on experience with the backend physical design flows, from a synthesized netlist all the way to layout completion for ASIC chip tapeout.

In the lab, the instructor will explain the tools used primarily for the placement and route part using IC Compiler (ICC). Other tools will be integrated within the flow but are available for students to practice on their own.

Topics include:

  • Physical design flow and synthesis
  • Floorplanning and pin assignment
  • Placement and clock-tree synthesis
  • Routing and optimization
  • Wire and extraction
  • Timing
  • Physical verification
  • Tapeout

Skills Needed: Basic knowledge of backend design flow. Hands-on experience with Linux/Unix will be required for lab exercises.

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