5613013

This Program is Perfect For

  • Hardware design and verification engineers aiming to specialize in VLSI and ASIC development
  • Professionals seeking depth in either front-end logic or back-end physical design
  • Working professionals and international students needing structured, flexible credentialing
  • Engineers and technologists preparing to meet the growing global semiconductor workforce demand

Next Info Session: April 2, 6 p.m.

Learn next-level VLSI design skills for top Silicon Valley companies

UCSC Silicon Valley Extension Silicon Chip Design & Semiconductor Engineering professional certificate program provides students with the core design skills they need to work at top companies in the Valley. Both established and aspiring engineers develop new skills, gain insight into digital and analog design techniques and methodologies, and learn from our expert faculty.

Integrated circuit curriculum

You'll explore ASIC, semiconductor, EDA, device, and integrated circuits. In our VLSI lab, our instructors will give you the opportunity to get hands-on experience with hardware specification, logic design, verification, synthesis, physical implementation, circuit design, integrated circuit product testing, and the latest EDA tools on Linux.

Two tailored elective tracks

  • Track 1: Front-end Design
    For professionals pursuing careers in application-specific integrated circuits (ASIC) architectural definitions and logic designs for its implementation.
  • Track 2: Back-end Design
    For professionals interested in the physical implementations of ASIC designs from synthesis to silicon.

Certificate program objectives

  • Implement Verilog modeling of digital logic
  • Write assertions for formal verification using SystemVerilog
  • Build an advanced UVM verification environment
  • Understand and implement DFT concepts in an ASIC design
  • Complete practical designs with Xilinx FPGAs
  • Implement a design from RTL to GDS

Access to premier tools

Using premier industry tools from Cadence, OpenROAD, Siemens, and Synopsys, you’ll learn front-end and back-end ASIC design and leave the classroom ready to apply new skills at your job.

Badge-silicon-cihp-design-semiconductor-engineering-certific
synopsys-300.jpg
Cadence_Logo_300px.jpg
siemens-2-300 copy.jpg
openroad-300.jpg

Courses

Program Requirements

Total: 5 courses (minimum 15 quarter units)

  • 3 required courses (9 quarter units)
  • 2 elective courses (minimum 6 quarter units)
  • End with certificate of completion review.

view COURSE Calendar

See the Syllabus Library
1. Core Course(s): (Choose Three)
Title units Fall Spring Summer Winter
Advanced Verification with SystemVerilog OOP Testbench 3.0 Live-Online
System and Functional Verification Using UVM (Universal Verification Methodology) 3.0 Flexible Live-Online
SystemVerilog Assertions and Formal Verification 3.0 Flexible
Practical DFT Concepts for ASICs, SoC and SiP 3.0 Live-Online, Flexible
AI for Autonomous Driving Systems: Concepts to FPGA 3.0 Live-Online
2. Electives: Front-End
Title units Fall Spring Summer Winter
Analog IC Design, Introduction 3.0 Live-Online
Digital Logic Design Using Verilog 3.0 Flexible
High Speed Interface Techniques 3.0 Flexible
Embedded System Hardware Architectures, Introduction 3.0 Flexible
High-Performance Computer Architecture 3.0 Flexible
Wireless Infrastructure: from Antenna Design to 5G, Fundamentals 3.0 Flexible
IO Concepts and Protocols: PCI Express and Ethernet 3.0 Live-Online
3. Electives: Back-End
Title units Fall Spring Summer Winter
Comprehensive Signal and Power Integrity for High-Speed Digital Systems 3.0 Live-Online
Practical Design with Xilinx FPGAs 3.0 Flexible
Physical Design Flow From Netlist to GDSII 3.0 Flexible
Timing Closure in Silicon IC Design 3.0 Flexible
High Speed Interface Techniques 3.0 Flexible
Introduction to VLSI and ASIC Design 3.0 Flexible
3D IC Packaging and Physical Verification 3.0 Flexible
Practical Design and Implementation of VLSI Memory Devices 3.0
ASIC Physical Design, Advanced 3.0
4. Completion Review:
Title units Fall Spring Summer Winter
Silicon Chip Design & Semiconductor Engineering Certificate Completion Fee
5. Related Workshops
Title units Fall Spring Summer Winter
Semiconductor Design and Innovation Workshop Series: RISC-V: Understanding Computer Architecture Flexible
Semiconductor Design and Innovation Workshop Series: High-Precision GHz Op Amp Design
Semiconductor Design and Innovation Workshop Series: Timing Constraint Management for Modern System On Chip

1. Core Course(s): (Choose Three)

Advanced Verification with SystemVerilog OOP Testbench
VLSI.X400
$980
You may enroll in this offering at any time.
Keshav Kannan
Keshav Kannan
Jun. 25 - Sep. 10, Thu, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X400.(27)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 06-25-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-16-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-03-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-10-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

Two "no meeting" dates TBD. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A course in SystemVerilog and knowledge of VHDL, Verilog, C/C++, and some hardware verification experience. Ability to install and configure open-source software on own computers.
Summer
System and Functional Verification Using UVM (Universal Verification Methodology)
VLSI.X410
$980
You may enroll in this offering at any time.
Benjamin Ting
Benjamin Ting
Apr. 7 - Jun. 23, Tue, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X410.(35)
Schedule
Date Start Time End Time Meeting Type Location
Tue, 04-07-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-14-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-21-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-28-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-05-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-12-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-19-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-26-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-02-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-09-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-16-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-23-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

2 "no meetings" TBA. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Textbooks:

"UVM Testbench Workbook"

"System and Functional Verification Using UVM" 

Note: Both books listed above are required for the course. These books are study guides that contain extensive course notes and step-by-step methodology development practices. Shipment by publisher may take 1-2 weeks.

Short descriptions of weekly homework and partial source code will be distributed in class at no additional expense to enrolled students.

The course is graded by Final Project only - homework assignments are not part of the final grade.

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X400: Advanced Verification with SystemVerilog OOP Testbench

Skills Needed:

  • Students should have experience with object-oriented programming, C/C++, or have taken "Advanced Verification with SystemVerilog OOP Testbench" course. Prerequisite topics will not be repeated here. Hardware verification experience is helpful.
You may enroll in this offering at any time.
Benjamin Ting
Benjamin Ting
Jun. 18 - Sep. 3, Thu, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X410.(36)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 06-18-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 06-25-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-16-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-03-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

2 "no meetings" TBA. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Textbooks:

"UVM Testbench Workbook"

"System and Functional Verification Using UVM" 

Note: Both books listed above are required for the course. These books are study guides that contain extensive course notes and step-by-step methodology development practices. Shipment by publisher may take 1-2 weeks.

Short descriptions of weekly homework and partial source code will be distributed in class at no additional expense to enrolled students.

The course is graded by Final Project only - homework assignments are not part of the final grade.

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X400: Advanced Verification with SystemVerilog OOP Testbench

Skills Needed:

  • Students should have experience with object-oriented programming, C/C++, or have taken "Advanced Verification with SystemVerilog OOP Testbench" course. Prerequisite topics will not be repeated here. Hardware verification experience is helpful.
Spring
Summer
SystemVerilog Assertions and Formal Verification
VLSI.X411
$980
You may enroll in this offering at any time.
Mandar M Munishwar
Mandar M Munishwar
Jun. 15 - Aug. 24, Mon, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X411.(18)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 06-15-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-22-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-29-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-06-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-13-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-20-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-03-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-10-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-17-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-24-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

No meeting on July 27, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Note: Students are required to bring laptops for coursework.

Required Tools & Materials: Access to a Windows, Mac, or Linux computer and the ability to install vpn software is required.  Students are required to bring laptops for coursework.

Summer
Practical DFT Concepts for ASICs, SoC and SiP
VLSI.X409
$980
You may enroll in this offering at any time.
Rajesh Y Pendurkar
Rajesh Pendurkar
Mar. 30 - Jun. 8, Mon, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X409.(16)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 03-30-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 04-06-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 04-13-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 04-20-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 04-27-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 05-04-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 05-11-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 05-18-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-01-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-08-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

3/11/26: Format change for first two sessions. See full schedule for details.

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

No meeting May 25, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:
VLSI Test Principles & Architectures: Design for Testability, Laung-Terng Wang, et al., Morgan Kaufmann, 2006, ISBN-10: 0123705975, ISBN-13: 978-0123705976.

Recommended Tools & Materials:
Digital Systems Testing and Testable Design; Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman; Wiley-IEEE Press ; 1994-09-27. ISBN: 9780780310629 
Important Note: If you have a previous edition of this book, you do not need to repurchase a more current version for this course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A working knowledge of digital logic design is recommended. 
Spring
AI for Autonomous Driving Systems: Concepts to FPGA
VLSI.X416
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter

2. Electives: Front-End

Analog IC Design, Introduction
VLSI.X401
$880
You may enroll in this offering at any time.
Mehrdad Peyvan
Mehrdad Peyvan
May. 2 - Jul. 18, Sat, 9:00am - 12:00pm
  • Live-Online Attend via Zoom at scheduled times.
VLSI.X401.(21)
Schedule
Date Start Time End Time Meeting Type Location
Sat, 05-02-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 05-09-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 05-16-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 05-30-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 06-06-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 06-13-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 06-20-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 06-27-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 07-11-2026 9:00am 12:00pm Live-Online REMOTE
Sat, 07-18-2026 9:00am 12:00pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meetings on May 23, 2026 and July 4, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: LTSpice is needed for the class.  Access will be provided.

 

||

Prerequisites / Skills Needed

Skills Needed:

  • Basic knowledge of microelectronics circuits, semiconductor devices and physics. Experience with UNIX/Linux systems and commands is required for the lab.
Spring
Digital Logic Design Using Verilog
VLSI.X404
$980
You may enroll in this offering at any time.
Parag Bhatt
Parag Bhatt
Apr. 16 - Jun. 18, Thu, 6:00pm - 9:00pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X404.(18)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 04-16-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 04-23-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 04-30-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-07-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-14-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-21-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-28-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 06-04-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 06-11-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 06-18-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tool: Verilog Simulator, and Synthesis tools.
Please see Modules in Canvas on how to access the tools.  

||

Prerequisites / Skills Needed

Skills Needed:

  • Knowledge of basic logic design and familiarity with a high-level programming language (e.g., C) and use of a text editor.
Spring
High Speed Interface Techniques
VLSI.X405
$820
You may enroll in this offering at any time.
Edison Fong
Edison Fong
Apr. 7 - Jun. 9, Tue, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X405.(18)
Schedule
Date Start Time End Time Meeting Type Location
Tue, 04-07-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-14-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-21-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-28-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-05-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-12-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-19-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-26-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-02-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-09-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A basic course in circuit design and understanding of basic electromagnetic physics.
Spring
Embedded System Hardware Architectures, Introduction
EMBD.X415
$820
You may enroll in this offering at any time.
Michael A. Wang
Michael Wang
Mar. 30 - Jun. 8, Mon, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
EMBD.X415.(17)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 03-30-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 04-06-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 04-13-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 04-20-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 04-27-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 05-04-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 05-11-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 05-18-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-01-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-08-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

No meeting May 25, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: None

Recommended Tools & Materials:
Embedded Systems Architecture: A Comprehensive Guide for Engineers and Programmers, 2nd Edition, Noergaard, Tammy, Newnes, 2012, ISBN: 978-0123821966.

||

Prerequisites / Skills Needed

Skills Needed:

  • Some familiarity with the hardware components of a computer system is required.
Spring
High-Performance Computer Architecture
VLSI.X415
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
Wireless Infrastructure: from Antenna Design to 5G, Fundamentals
EMBD.X419
$775 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
IO Concepts and Protocols: PCI Express and Ethernet
EMBD.X406
$950 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Fall

3. Electives: Back-End

Comprehensive Signal and Power Integrity for High-Speed Digital Systems
EMBD.X400
$980
You may enroll in this offering at any time.
Kalyan Rapolu
Kalyan Rapolu
Jun. 25 - Aug. 27, Thu, 6:30pm - 9:30pm
  • Live-Online Attend via Zoom at scheduled times.
EMBD.X400.(17)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 06-25-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-16-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: None

Recommended Tools & Materials:
Advanced Signal Integrity for High-Speed Digital Designs, Stephen H. Hall and Howard L. Heck, John Wiley & Sons, 2011, ISBN: 9781118210680.

Principles of Power Integrity for PDN Design - Simplified, Larry D. Smith and Eric Bogatin, Prentice Hall, 2017, ISBN: 9780132735629.

||

Prerequisites / Skills Needed

Prerequisites:

  • EMBD.X409: Printed Circuit Board Design for Signal Integrity and EMC Compliance

Skills Needed:

  • Students must have a basic understanding of signal integrity, electromagnetic compatibility, printed circuit boards or packages.
Summer
Practical Design with Xilinx FPGAs
EMBD.X408
$910
You may enroll in this offering at any time.
Joanna Mapel
Joanna Mapel
Jun. 15 - Aug. 17, Mon, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
EMBD.X408.(17)
Schedule
Date Start Time End Time Meeting Type Location
Mon, 06-15-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-22-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 06-29-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-06-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-13-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-20-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 07-27-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-03-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-10-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 08-17-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:
VHDL for Logic Synthesis, Authors: Andrew Rushton, Publisher: John Wiley & Sons, Publication Date: 2011-04-25, ISBN: 9780470688472

Students are required to purchase a Zynq-based board for their project (approximately $100, not included in the tuition). Detailed board information and instruction will be provided on the first night of class.

Recommended Texts:
The Verilog(R) Hardware Description Language, Authors: Donald Thomas, Philip Moorby, Publisher: Springer Science & Business Media, Publication Date: 2008-09-11, ISBN: 9780387853444

The Design Warrior's Guide to FPGAs, Authors: Clive Maxfield, Publisher: Elsevier, Publication Date: 2004-06-16, ISBN: 9780080477138

||

Prerequisites / Skills Needed

Skills Needed:

  • Experience with logic design of digital systems or equivalent knowledge.
Summer
Physical Design Flow From Netlist to GDSII
VLSI.X408
$980
You may enroll in this offering at any time.
Shree Laguduva
Shree Laguduva
Jun. 5 - Aug. 21, Fri, 6:00pm - 9:00pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X408.(16)
Schedule
Date Start Time End Time Meeting Type Location
Fri, 06-05-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 06-12-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 06-26-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 07-10-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 07-17-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 07-24-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 07-31-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 08-07-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 08-14-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Fri, 08-21-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience.

No meeting June 19 and July 3, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Recommended Text: 
Physical Design Essentials: An ASIC Design Implementation Perspective, Khosrow Golshan, Springer, 2010, ISBN-10: 144194219X, ISBN-13: 978-1441942197.

SoC Physical Design: A Comprehensive Guide, Chakravarthi and Koteshwar, Springer, 2022, ISBN: 9783030981112

CMOS VLSI Design: A Circuits and Systems Perspective, Weste and Harris, Pearson, 2015, ISBN: 9789332559042

||

Prerequisites / Skills Needed

Skills Needed:

  • Basic knowledge of backend design flow. Hands-on experience with Linux/Unix will be required for lab exercises. 
Summer
Timing Closure in Silicon IC Design
VLSI.X414
$980
You may enroll in this offering at any time.
Jignesh Shah
Jignesh Shah
Apr. 10 - Jun. 12, Fri, 5:00pm - 8:00pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X414.(16)
Schedule
Date Start Time End Time Meeting Type Location
Fri, 04-10-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 04-17-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 04-24-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 05-01-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 05-08-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 05-15-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 05-22-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 05-29-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 06-05-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
Fri, 06-12-2026 5:00pm 8:00pm Flexible SANTA CLARA / REMOTE
 

3/13/26: Course time change. See full schedule for details.

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:
Static Timing Analysis for Nanometer Designs: A Practical Approach, Bhasker and Chadha, Springer, 2009, ISBN-13: 978-0387938196.

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X403: Introduction to VLSI and ASIC Design

Skills Needed:

  • Linux/Unix skills are required for lab exercises.
Spring
High Speed Interface Techniques
VLSI.X405
$820
You may enroll in this offering at any time.
Edison Fong
Edison Fong
Apr. 7 - Jun. 9, Tue, 6:30pm - 9:30pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X405.(18)
Schedule
Date Start Time End Time Meeting Type Location
Tue, 04-07-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-14-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-21-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 04-28-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-05-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-12-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-19-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 05-26-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-02-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Tue, 06-09-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

||

Prerequisites / Skills Needed

Skills Needed:

  • A basic course in circuit design and understanding of basic electromagnetic physics.
Spring
Introduction to VLSI and ASIC Design
VLSI.X403
$980
You may enroll in this offering at any time.
Rajiv Dave, Instructor, Silicon Chip Design & Semiconductor Engineering
Rajiv Dave
Apr. 4 - Jun. 13, Sat, 9:00am - 12:00pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X403.(12)
Schedule
Date Start Time End Time Meeting Type Location
Sat, 04-04-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 04-11-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 04-18-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 04-25-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 05-02-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 05-09-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 05-16-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 05-30-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 06-06-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
Sat, 06-13-2026 9:00am 12:00pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

No meeting on May 23, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:

A Practical Approach to VLSI System on Chip (SoC) Design, Chakravarthi, Veena S., Springer Nature, 2022,  ISBN: 9783031183638.

||

Prerequisites / Skills Needed

Skills Needed:

  • General understanding of digital logic.
  • Lab exercises require some knowledge of Linux.
Spring
3D IC Packaging and Physical Verification
VLSI.X418
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
Practical Design and Implementation of VLSI Memory Devices
VLSI.X417
Currently no classes scheduled. Would you like to be notified when a class is available?
ASIC Physical Design, Advanced
VLSI.X402
Currently no classes scheduled. Would you like to be notified when a class is available?

4. Completion Review:

Silicon Chip Design & Semiconductor Engineering Certificate Completion Fee
O-CE0186
$95
You may enroll in this offering at any time.
Mar. 28, , All Day
O-CE0186.(017)
Schedule
 

Please enroll in the VLSI and Semiconductor Engineering Certificate Completion Fee only when all of the certificate requirements have been met and your final grades are posted.

5. Related Workshops

Semiconductor Design and Innovation Workshop Series: RISC-V: Understanding Computer Architecture
VLSI.800_W2
$95 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Fall
Semiconductor Design and Innovation Workshop Series: High-Precision GHz Op Amp Design
VLSI.800_W3
$95 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Semiconductor Design and Innovation Workshop Series: Timing Constraint Management for Modern System On Chip
VLSI.800_W1
Currently no classes scheduled. Would you like to be notified when a class is available?

Recommended course sequence

Requisite expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Planning your coursework

Beginners should take introductory courses before advanced. Other courses can be taken based on your interests and professional levels.

Please review course descriptions—Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Related electives

  • Embedded System Hardware Architectures, Introduction (3.0)
  • System Design for Low Power Management (1.0)

Substitutions | Shared credits

You may take one elective outside the certificate curriculum if you receive prior approval from the Academic Services Department.

Some technology courses may be listed in more than one program. However, only one course may be shared between two certificate programs unless otherwise noted.

To receive your certificate

Upon completion of the course sequence, you may request your Semiconductor Engineering Certificate Completion Review.

Demo

Establish Candidacy

1. Complete a Course

Complete at least one course in your selected program.

2. Declare Candidacy

Declaring candidacy is free. Click “Enroll” and follow the steps to submit your application online.

3. Complete Requirements

You must establish candidacy in the certificate program before enrolling in the Certificate Completion Review.

Requisite knowledge

Technical expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Please review course descriptions

Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Grade requirements

Please note that only letter grades of C or higher may be applied to a certificate, and in some programs, students may have more stringent requirements. Students in most employer- and government-sponsored payment programs, such as workforce development, as well as international students on F-1 visas, need to maintain a B average to meet their requirements.

See Grading and Credits Policy for further information.

Instructors

Program Chair
Arvind Vidyarthi

Arvind Vidyarthi

Chair | Sr. Dtr., Silicon Design Implementation & Methodology, Altera

ARVIND VIDYARTHI, M.S.E.E., senior director of silicon design implementation and methodology at Altera (an Intel company), has 20+ years of industry experience in chip implementation in various major semiconductor companies such as Sun Microsystems, AMD, and Nvidia. He has successfully managed chip design with multiple tapeouts at Intel and is familiar with all major implementation tools and methodologies. He is passionate about ML/AI in chip design and implementation for performance, power, and area (PPA) and turn-around-time improvement. He has served as chair of the UCSC Silicon Valley Extension Silicon Chip Design & Semiconductor Engineering program since 2022.

Abhay Singh
Abhay Singh
Silicon Operations and Partnerships, Google
Ajit A Natarajan
Ajit Natarajan
Sr. Software Engineer, Google
Benjamin Ting
Benjamin Ting
Principal Engineer, Microsoft
Bharat Patel
Bharat Patel
Director/Technologist in the Programmable Solutions Group, Intel
Edison Fong
Edison Fong
RF Engineer and Analog Engineer, Consultant
Emiliano Morini
Emiliano Morini
Principal Formal Verification Engineer, NVIDIA
Ibrahim Delibalta
Ibrahim Delibalta
Sr. Director of SoC Design at Intel Corp.
Jignesh Shah
Jignesh Shah
Principal STA & CAD Engineer, d-Matrix
Joanna Mapel
Joanna Mapel
Field Application Engineer, Xilinx/AMD at Avnet
Kalyan Rapolu
Kalyan Rapolu
Senior Solutions Engineer, Keysight
Keshav Kannan
Keshav Kannan
Verification Lead, Intel Corporation
Lavanya Aryasomayajula
Lavanya Aryasomayajula
Principal Engineer, onsemi
Mandar M Munishwar
Mandar M Munishwar
Formal Verification Architect, Intel Data Center and AI Division
Mehrdad Peyvan
Mehrdad Peyvan
Senior Application Manager, Analog Devices
Michael A. Wang
Michael Wang
Director of Business Development, ISSI Integrated Silicon Solution Inc.
Parag Bhatt
Parag Bhatt
VP of Engineering, Signature IP Corporation
Rajesh Y Pendurkar
Rajesh Pendurkar
Director of Engineering, Capgemini
Rajiv Dave, Instructor, Silicon Chip Design & Semiconductor Engineering
Rajiv Dave
Senior Product Manager/Principal Engineer
Samit Mehrotra
Samit Mehrotra
Microarchitect, Intel Corp.
Shree Laguduva
Shree Laguduva
ASIC Physical Design Engineer, Apple

Certificate Program Advisory Committee

JEFFERY GOODING, MSEE
Account Technology Executive, Cadence Design Systems

SAM HUYNH, Ph.D., MSEE
Principal Member of Technical Staff, AMD
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JIM SCHULTZ, B.S.
Product Marketing Manager, Digital Design Implementation, Synopsys Inc.

MANDAR MUNISHWAR, B.E.
Formal Verification Architect, Intel Data Center and AI Division
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JOSE RENAU, Ph.D.
Professor, Computer Science and Engineering, Jack Baskin School of Engineering, UC Santa Cruz
Consultant, Esperanto Technologies, Inc.

BENJAMIN TING, M.S.E.E.
Principal Engineer, Micron Technology
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

ARVIND VIDYARTHI, M.S.E.E.
Senior Director, Silicon Design Implementation and Methodology, Altera (an Intel company)|
Program Chair | Instructor, Silicon Chip Design and Semiconductor Engineering

Related Programs

Demo