Build advanced OOP testbenches with SystemVerilog for robust, coverage-driven verification.
SystemVerilog is the industry IEEE-1800 standard combining the hardware description language and hardware verification language. This course focuses on the use of advanced verification features in SystemVerilog. Students will learn the step-by-step processes of creating flexible verification components, which form the basis of modern industry-standard methodologies such as UVM (Universal Verification Methodology). They will also gain experience developing an industrial-strength object-oriented programming (OOP) testbench that is layered, configurable, constrained-random, and coverage-driven.
The course starts with a brief review of SystemVerilog language semantics and simulation fundamentals such as event ordering, delta cycles and race conditions, which will then feed into closely related entities in program block, clocking block, and interfaces. Students will learn how to develop a complete verification environment by building flexible testbench components via the use of virtual interfaces, classes, mailboxes, dynamic arrays, and queues, etc. Functional coverage in the form of covergroup, coverpoint, and SystemVerilog Assertion (SVA), will round up the development of a complete verification environment. You will become familiar with the flexibility of an OOP-centric technique, the power of constrained random verification and the use of functional coverage tools to ensure the success of a verification project.
Concepts introduced in class are reinforced in the lab. In addition to in-class hands-on labs and weekly take-home assignments, students will work on a required project to build an advanced OOP testbench and verification environment for a selected application (such as a 10G Ethernet MAC design), with transaction-level and layered architecture. Students will form a project team, create a test plan, develop an OOP-centric verification environment, perform functional coverage, and submit a complete project report. This course builds the foundation for the course "System and Functional Verification Using UVM (Universal Verification Methodology)."
A course in SystemVerilog and knowledge of VHDL, Verilog, C/C++, and some hardware verification experience. Ability to install and configure open-source software on own computers.
Students may still enroll if they missed the 1st class session. However, they need to communicate with the instructor via Canvas and catch up on all missed work prior to the 2nd class meeting.
8/27/2025: Change of schedule and instructor. Please review full schedule for details.
Students may enroll until the second meeting.
This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.
Electronic Course Materials: You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Required Texts: (Click on links to order)
"Advanced Verification using SystemVerilog OOP Testbench"
Note: Both books listed above are required for the course. These books are study guides that contain extensive course notes and step-by-step methodology development practices. Shipment by publisher may take 1-2 weeks.
Short descriptions of weekly homework and partial source code will be distributed in class at no additional expense to enrolled students.
The course is graded by Final Project only - homework assignments are not part of the final grade.
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.
To see all meeting dates, click “Full Schedule” below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
