RAJESH PENDURKAR, Ph.D., an accomplished researcher and computer design scientist, is an engineering leader and an entrepreneur with more than 20 years’ experience in hardware and software engineering. He has focused on high-end microprocessor design and test, system on chip (SoC) architecture, design, verification, DFx, CAD, software algorithms, product qualification and ramp-up. His innovative leadership has been demonstrated at multinational tech leaders such as Sun Microsystems, Broadcom Inc., Wipro Ltd. and RMI Corp., a Silicon Valley startup in the semiconductor space. His research interests include design for debug, built-in self-test, optimization algorithms, and machine learning. With more than 20 publications and six patents in memory test software, Pendurkar is a senior member of IEEE and has presented numerous times at the IEEE conferences and workshops. He is founder of TriSquare Sense LLC, an IC product development and consulting firm, and has consulted on ASIC Design at Intel, and Google and helped drive hardware strategy at a startup. Pendurkar has a bachelor’s degree in electronics and telecommunications engineering from University of Pune, India, a master’s in computer systems engineering from Northeastern University, an MBA from Marshall School of Business, University of Southern California, and a doctorate in computer engineering from Georgia Institute of Technology.
Practical DFT Concepts for ASICs, SoC and SiP
- Flexible Attend in person or via Zoom at scheduled times.
| Date | Start Time | End Time | Meeting Type | Location |
|---|---|---|---|---|
| Mon, 03-30-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 04-06-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 04-13-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 04-20-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 04-27-2026 | 6:30pm | 9:30pm | Live-Online | REMOTE |
| Mon, 05-04-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 05-11-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 05-18-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 06-01-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
| Mon, 06-08-2026 | 6:30pm | 9:30pm | Flexible | SANTA CLARA / REMOTE |
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.
No meeting May 25, 2026. To see all meeting dates, click "Full Schedule" below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Required Text:
VLSI Test Principles & Architectures: Design for Testability, Laung-Terng Wang, et al., Morgan Kaufmann, 2006, ISBN-10: 0123705975, ISBN-13: 978-0123705976.
Recommended Text:
Digital Systems Testing and Testable Design; Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman; Wiley-IEEE Press ; 1994-09-27. ISBN: 9780780310629
Important Note: If you have a previous edition of this book, you do not need to repurchase a more current version for this course.