Method
Live-Online
Term
SPRING
Units
3.0 QUARTER UNITS
Estimated Cost
$980

Skills you will gain

  • Delay Analysis and Characterization: Analyze and model delays in combinational and sequential circuits for optimized design performance.
  • Static Timing Analysis Expertise: Master industry-standard STA techniques for block-level and full-chip designs.
  • Timing Constraint Development: Write, debug, and optimize clock constraints and exceptions for effective timing closure.
  • Engineering Change Order (ECO) Implementation: Apply ECO methods to fix critical timing paths and meet silicon performance goals.
  • Advanced Timing Concepts: Understand key topics like PVTs, OCV, CRPR, crosstalk, and clock domain crossing (CDC) for robust design execution.

Course Description


As transistor technology becomes increasingly complex in the sub-nanometer process, the timing signoff of designs such as ASIC, FPGA, GPU, and SoC becomes more challenging.

 

In this course, you will learn industry-standard timing methodologies and techniques used during design implementation to achieve targeted clock frequency and ensure manufacturing yield of successful silicon.

The course begins with foundational concepts, including transistor topology, delay modeling through digital gates, and setup and hold characterization. You will gain hands-on exposure to clock constraints, exceptions, and what-if analysis, and learn how to address timing violations in ECO (Engineering Change Order) mode.

Advanced topics include signal integrity (SI) analysis and prevention, process variations, hierarchical and flat analysis, and STA (Static Timing Analysis) margin. The instructor will share practical examples of block-level and full-chip timing closure, budgeting, and debugging skills. Students will also explore EDA tools and practice with small test cases.

By the end of the course, design engineers will be able to perform static timing analysis using PrimeTime, Genus, OpenROAD, or any other STA tool during multiple phases of design implementation.

 

Learning Outcomes 
At the conclusion of the course, you should be able to:

  • Analyze and characterize delays in combinational & sequential circuits
  • Discuss in-depth knowledge of static timing analysis
  • Write and debug constraints
  • Drive timing closure for block or chip
  • Write ECOs
  • Explain how to fix critical timing paths
  • Define terms such as PVTs, OCV, CRPR, crosstalk, CDC, etc.

 

Skills Needed:

Linux/Unix skills are required for lab exercises.

Additional Information

AI* - This course teaches students how to use prompts with free AI chatbots such as Gemini and ChatGPT to develop and analyze scripts for STA tools. 

 

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X403: Introduction to VLSI and ASIC Design
Syllabus Library
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This course applies to these programs:

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