Method
Flexible
Term
FALL
Units
3.0 QUARTER UNITS
Estimated Cost
$980

Skills you will gain

  • Scan-Based Design Mastery: Build scan chains and apply test-smart synthesis using Synopsys DFT Compiler.
  • High-Coverage ATPG Implementation: Generate advanced test patterns with TetraMAX to detect hard-to-find faults.
  • Built-In Self-Test (BIST): Leverage LBIST and MBIST for efficient on-chip testing and reduced reliance on external testers.
  • Sequential Testing Techniques: Tackle non-scan flops using sequential ATPG and optimize DFT logic.
  • Nanometer-Scale Testing Strategies: Apply modern fault models, adaptive scan methods, and IP core testing best practices.

Course Description

Formerly "Practical DFT Concepts for ASICs: Nanometer Test Enhancements"

Testing application-specific integrated circuits (ASICs), system on chips (SOCs) and system in packages (SIP) is becoming very challenging in today's advanced process technologies/nodes. The dense spacing of lines on silicon, gigahertz clock rates, newly-emerging fault classes—these factors make it difficult to reach even 98% coverage. This course is ideal for integrated circuit (IC) designers seeking a deeper understanding of test issues, or test engineers wanting to stay current with emerging trends and tools.

This course is filled with engineering insights. It first builds a solid foundation in scan-based design —a necessary skill for understanding more recent techniques like delay-fault testing, scan compression, and built-in self test (BIST). Students will gain hands-on experience in building scan chains and generating test patterns, using Synopsys DFT Compiler (DFTC) and TetraMAX ATPG. You will learn advanced topics such as inserting multiple scan chains, employing sequential ATPG to handle non-scan flops, optimizing DFT logic, understanding LBIST and MBIST, and following nanometer trends in testing.

The systematic hands-on labs reinforce techniques introduced in lecture, and are packed with useful information and practical guidelines. By the conclusion of the course, you will be able to hand off a full-scan design and generate a high-coverage test program for nanometer ASIC.


Prerequisites / Skills Needed

A working knowledge of digital logic design is recommended.

Syllabus Library
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This course applies to these certificate programs:

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