Learn IC development with hands-on labs in RTL, DFT, synthesis, and packaging
With shrinking process technologies, today's silicon chips are so complex that few engineers and managers fully understand every phase in the IC development cycle.
This unique course provides an overview of all the steps in developing an ASIC, SoC, GPU or FPGA product. Key topics include transistor topology, standard cells, RTL synthesis, meeting timing, functional coverage, formal equivalence, physical design, signal integrity, DFT, chip tape-out, IC fabrication, and emerging packaging trends.
Through small hands-on labs and homework, students become familiar with the roles of architecture selection, micro architecture specification, synthesis, simulation, formal equivalence, and routing tools. The focus is on mostly-digital ASICs with multiple IP cores, low-power goals, and on-chip analog blocks.
Designed for professionals in the semiconductor field—whether experienced or entry-level—this course provides a deeper understanding of the product development process for silicon chips and SoCs. Knowledge gained in this course will improve cross-functional communication with other team members and prepare individuals for more rigorous study in the semiconductor design field.
