Learn IC development with hands-on labs in RTL, DFT, synthesis, and packaging
Skills you will gain
- Digital Design and Verification Flows: Understand the complete design and verification processes in digital design.
- Advanced Design Methodologies: Stay updated on the latest design technologies and methodologies used in VLSI and ASIC design.
- VLSI and FPGA Interview Readiness: Prepare to confidently address complex VLSI ASIC and FPGA-related interview questions.
- ASIC Development Flow: Gain a deep understanding of the intricacies of the ASIC development flow.
- Hands-on Lab Experience: Develop practical experience with architecture selection, microarchitecture, synthesis, simulation, and routing tools.
Course Description
With shrinking process technologies, today's silicon chips are so complex that few engineers and managers fully understand every phase in the IC development cycle.
This unique course provides an overview of all the steps in developing an ASIC, SoC, GPU or FPGA product. Key topics include transistor topology, standard cells, RTL synthesis, meeting timing, functional coverage, formal equivalence, physical design, signal integrity, DFT, chip tape-out, IC fabrication, and emerging packaging trends.
Through small hands-on labs and homework, students become familiar with the roles of architecture selection, micro architecture specification, synthesis, simulation, formal equivalence, and routing tools. The focus is on mostly-digital ASICs with multiple IP cores, low-power goals, and on-chip analog blocks.
Designed for professionals in the semiconductor field—whether experienced or entry-level—this course provides a deeper understanding of the product development process for silicon chips and SoCs. Knowledge gained in this course will improve cross-functional communication with other team members and prepare individuals for more rigorous study in the semiconductor design field.
Topics
- Overview of SoC (System on Chip) architectures
- Integration of IP cores
- Overcome the verification bottleneck
- How on-chip firmware code interacts with the chip’s hardware
- Digital logic gates, metal layers and vias, place & routing insights, noise avoidance, DFM issues, timing closure
- Business practices with silicon foundries: sort, shuttles, corner lots
- Comprehensive coverage of the chip design flow, from spec through tape-out to fabrication and packaging, equipping students for follow-on courses in RTL design, verification, DFT, and layout
Prerequisites / Skills Needed
- General understanding of digital logic.
- Lab exercises require some knowledge of Linux.
- Flexible Attend in person or via Zoom at scheduled times.
| Date | Start Time | End Time | Meeting Type | Location |
|---|---|---|---|---|
| Sat, 04-04-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 04-11-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 04-18-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 04-25-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 05-02-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 05-09-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 05-16-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 05-30-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 06-06-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
| Sat, 06-13-2026 | 9:00am | 12:00pm | Flexible | SANTA CLARA / REMOTE |
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.
No meeting on May 23, 2026. To see all meeting dates, click "Full Schedule" below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Required Text:
A Practical Approach to VLSI System on Chip (SoC) Design; Veena S. Chakravarthi; Springer Nature; 2022. ISBN: 9783031183638
This course applies to these programs: