As artificial intelligence teaches machines to think, it also challenges us to rethink what it means to be human—because even as AI predicts the road ahead, only we decide where it truly leads.

About

PARAG BHATT, M.S., president of an AI startup in stealth mode, is an accomplished engineering leader and educator with over 25 years of experience in the semiconductor industry. He specializes in ASIC design, verification, and SoC technologies and combines deep technical expertise with a passion for teaching. Former vice president of Engineering at Signature IP Corp., he has successfully mentored global teams, developed training programs, and delivered high-performance solutions, including PCIe and CXL controllers and customizable NoC architectures. Bhatt has a proven ability to bridge industry practices and academic learning and has led more than 50 projects and advanced FPGA adaptations and IP portfolios. He has a master's degree in Electrical and Computer Engineering from Oklahoma State University and is dedicated to fostering student success by delivering industry-relevant knowledge and preparing the next generation of engineers.

Parag Bhatt's courses currently open for enrollment

Digital Logic Design Using Verilog

VLSI.X404
$980
Parag Bhatt
Apr. 16 - Jun. 18, Thursday, 6:00pm - 9:00pm
  • Flexible Attend in person or via Zoom at scheduled times.
VLSI.X404.(18)
Schedule
Date Start Time End Time Meeting Type Location
Thu, 04-16-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 04-23-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 04-30-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-07-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-14-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-21-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 05-28-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 06-04-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 06-11-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
Thu, 06-18-2026 6:00pm 9:00pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tool: Verilog Simulator, and Synthesis tools.
Please see Modules in Canvas on how to access the tools.  

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Prerequisites / Skills Needed

Skills Needed:

  • Knowledge of basic logic design and familiarity with a high-level programming language (e.g., C) and use of a text editor.
Associated Program(s)
Silicon Chip Design & Semiconductor Engineering