Design and debug FPGA projects using Xilinx Vivado on Virtex-7, Artix, Kintex, and Zynq.
Skills you will gain
- Implement a practical design on Xilinx hardware
- Debug a design on Xilinx hardware
- Use the Xilinx Vivado tool
- Explain common Xilinx FPGA features and how to use them in the software tool
- Demonstrate a broader view of FPGA applications and an understanding of programmable products in the market
Course Description
Field Programmable Gate Arrays (FPGAs) are configurable logic devices with programmable links. They allow you to implement, update, and ship ASICs with low non-recurring engineering costs and are widely used in system design. This course offers a practical introduction to programmable logic design with Xilinx FPGAs, emphasizing design implementation. The course focuses on improving design methods to advance overall design quality; in essence, to bulletproof a design.
Standard logic designs translate automatically and effectively to the world of field programmable logic devices. The course covers common methods based on design constraints used in most design software. You will learn design implementations such as clocking (which creates various clock frequencies from an external reference), including how to handle control and data signals migrating across different clock domains, how to manage clock jitter and debounce input asynchronous signals. You will also learn to manage ground bounce and control power dissipation, while including considerations for safety and security. Practical design examples include discussions of RAM, DSP blocks, basic fabric and A/D converters.
The course places an architectural focus on the Virtex-7, Artix and Kintex families, as well as the Zynq programmable system on a chip. In-class demonstrations and student design projects will feature the Xilinx Vivado Webpack design software. By the end of the course, you should be able to complete practical designs with Xilinx FPGAs and understand design and timing reports. The course includes a student project with design tools; real device implementation or programming is optional.
Note(s):
Students are required to purchase a Zynq-based board for their project (approximately $100, not included in the tuition). Detailed board information and instruction will be provided on the first night of class. Experience with logic design of digital systems or equivalent knowledge.Prerequisites / Skills Needed
- Flexible Attend in person or via Zoom at scheduled times.
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.
To see all meeting dates, click "Full Schedule" below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Required Text:
VHDL for Logic Synthesis, Authors: Andrew Rushton, Publisher: John Wiley & Sons, Publication Date: 2011-04-25, ISBN: 9780470688472
Recommended Texts:
The Verilog(R) Hardware Description Language, Authors: Donald Thomas, Philip Moorby, Publisher: Springer Science & Business Media, Publication Date: 2008-09-11, ISBN: 9780387853444
The Design Warrior's Guide to FPGAs, Authors: Clive Maxfield, Publisher: Elsevier, Publication Date: 2004-06-16, ISBN: 9780080477138
