Rajiv Dave

RAJIV DAVE, M.S.C.E., is an experienced senior product manager and principal engineer passionate about developing next generation physical design solutions and has led the end-to-end design and development of an AI/Machine learning solution for tool development. He has worked at Synopsys, Nanovata and Avant! as a product specialist role in physical design implementation. 

Dave has 25 years of experience in digital design implementation development and led solutions for place and route EDA tools, ensuring advanced node development for TSMC, Samsung, Intel, and Global foundries. He has led multiple teams focusing on design planning, clock tree synthesis, timing, signal integrity, signal EM, extraction, placement, routing, post-route optimization, leakage optimization, signoff optimization, flip chip and development of the Synopsys RTL Architect tool. He has also published a routing patent. 

Lately he has led the development and deployment of professional training solutions at Synopsys. He has successfully designed and developed engineering certification courses for RTL design, RTL synthesis, design for test, physical synthesis, analog circuit & layout design, signoff and manufacturing engineers.