Master ASIC physical design flow from netlist to GDS-II layout.
With shrinking process technologies, physical design is becoming extremely challenging. Physical designers are responsible for producing high quality design tapeout, and an understanding of all aspects of physical design from synthesis to tapeout is critical to success. This course is an introduction to the ASIC physical design flow and tools from netlist (gate level) to GDS-II (fractured data).
After an overview of the ASIC physical design flow and synthesis, the course starts with floor planning and block pin assignment. It then covers placement and clock-tree synthesis, followed by routing, and post-route optimization. You will learn RC extraction, static timing analysis, and physical verification. Upon completion of this course, you will possess the essential knowledge and hands-on experience with the backend physical design flows, from a synthesized netlist all the way to layout completion for ASIC chip tapeout.
For the labs, the instructor will explain the tools used primarily for the placement and route part using IC Compiler (ICC). Other tools such as OpenROAD will be integrated within the flow but are available for students to practice on their own.
Basic knowledge of backend design flow. Hands-on experience with Linux/Unix will be required for lab exercises.
This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience.
No meeting on March 27, 2026. To see all meeting dates, click "Full Schedule" below.
You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.
Recommended Text:
Physical Design Essentials: An ASIC Design Implementation Perspective, Khosrow Golshan, Springer, 2010, ISBN-10: 144194219X, ISBN-13: 978-1441942197.
SoC Physical Design: A Comprehensive Guide, Chakravarthi and Koteshwar, Springer, 2022, ISBN: 9783030981112
CMOS VLSI Design: A Circuits and Systems Perspective, Weste and Harris, Pearson, 2015, ISBN: 9789332559042
