Method
Live-Online
Term
SUMMER
Units
3.0 QUARTER UNITS
Estimated Cost
$980

Skills you will gain

  • Mastery of ASIC Design Flow: Understand the full RTL-to-GDSII physical design pipeline, from synthesis to tapeout.
  • Hands-On Tool Experience: Gain practical skills using industry tools like IC Compiler and OpenROAD for placement and routing.
  • Floorplanning & Clock-Tree Synthesis: Learn key physical design steps including block placement, pin assignment, and CTS.
  • Static Timing & Verification: Apply RC extraction and static timing analysis to ensure performance and reliability.
  • Layout Completion for Tapeout: Generate a final GDSII layout from a synthesized netlist, ready for fabrication.

Course Description


With shrinking process technologies, physical design is becoming extremely challenging. Physical designers are responsible for producing high quality design tapeout, and an understanding of all aspects of physical design from synthesis to tapeout is critical to success. This course is an introduction to the ASIC physical design flow and tools from netlist (gate level) to GDS-II (fractured data).

After an overview of the ASIC physical design flow and synthesis, the course starts with floor planning and block pin assignment. It then covers placement and clock-tree synthesis, followed by routing, and post-route optimization. You will learn RC extraction, static timing analysis, and physical verification. Upon completion of this course, you will possess the essential knowledge and hands-on experience with the backend physical design flows, from a synthesized netlist all the way to layout completion for ASIC chip tapeout.

For the labs, the instructor will explain the tools used primarily for the placement and route part using IC Compiler (ICC). Other tools such as OpenROAD will be integrated within the flow but are available for students to practice on their own.


Learning Outcomes 
At the conclusion of the course, you should be able to

  • Explain the terms and acronyms used in Physical Design
  • Discuss the concept of Physical Design, ASIC design flow (RTL-to-GDS)
  • Demonstrate the core features of IC Compiler which is used during the course
  • Generate a GDS from an RTL design

 

Skills Needed:

Basic knowledge of backend design flow. Hands-on experience with Linux/Unix will be required for lab exercises.  

*This course may be applied to a certificate only if you are currently declared in a program.

Additional Information

AI* - This course will utilize AI to demonstrate how to begin writing scripts for EDA tools with the help of platforms like ChatGPT, Gemini, Grok, and Perplexity. 

Syllabus Library
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This course applies to these programs:

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