This Program is Perfect For

  • Hardware design and verification engineers aiming to specialize in VLSI and ASIC development
  • Professionals seeking depth in either front-end logic or back-end physical design
  • Working professionals and international students needing structured, flexible credentialing
  • Engineers and technologists preparing to meet the growing global semiconductor workforce demand

Program review underway

Important update for 2026-27

As we evolve our programs to reflect today’s technology landscape, the certificate in Silicon Chip Design & Semiconductor Engineering is under review and is not currently open for new enrollment. If you are enrolled in this certificate and are finishing up your courses, please reach out to us at extension@ucsc.edu. We will help you plan your journey. 

Courses are open to everyone

You are invited to build and strengthen your teaching skills by enrolling in individual courses.

 


Learn next-level VLSI design skills for top Silicon Valley companies

UCSC Silicon Valley Extension Silicon Chip Design & Semiconductor Engineering professional certificate program provides students with the core design skills they need to work at top companies in the Valley. Both established and aspiring engineers develop new skills, gain insight into digital and analog design techniques and methodologies, and learn from our expert faculty.

Integrated circuit curriculum

You'll explore ASIC, semiconductor, EDA, device, and integrated circuits. In our VLSI lab, our instructors will give you the opportunity to get hands-on experience with hardware specification, logic design, verification, synthesis, physical implementation, circuit design, integrated circuit product testing, and the latest EDA tools on Linux.

Two tailored elective tracks

  • Track 1: Front-end Design
    For professionals pursuing careers in application-specific integrated circuits (ASIC) architectural definitions and logic designs for its implementation.
  • Track 2: Back-end Design
    For professionals interested in the physical implementations of ASIC designs from synthesis to silicon.

Certificate program objectives

  • Implement Verilog modeling of digital logic
  • Write assertions for formal verification using SystemVerilog
  • Build an advanced UVM verification environment
  • Understand and implement DFT concepts in an ASIC design
  • Complete practical designs with Xilinx FPGAs
  • Implement a design from RTL to GDS

Access to premier tools

Using premier industry tools from Cadence, OpenROAD, Siemens, and Synopsys, you’ll learn front-end and back-end ASIC design and leave the classroom ready to apply new skills at your job.

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Courses

Program Requirements

Total: 5 courses (minimum 15 quarter units)

  • 3 required courses (9 quarter units)
  • 2 elective courses (minimum 6 quarter units)
  • End with certificate of completion review.

view COURSE Calendar

1. Core Course(s): (Choose Three)
Title units Fall Spring Summer Winter
System and Functional Verification Using UVM (Universal Verification Methodology) 3.0 Live-Online Live-Online
Advanced Verification with SystemVerilog OOP Testbench 3.0 Live-Online
SystemVerilog Assertions and Formal Verification 3.0 Flexible
AI for Autonomous Driving Systems: Concepts to FPGA 3.0 Live-Online
Practical DFT Concepts for ASICs, SoC and SiP 3.0 Live-Online, Flexible
2. Electives: Front-End
Title units Fall Spring Summer Winter
Embedded System Hardware Architectures, Introduction 3.0 Flexible
IO Concepts and Protocols: PCI Express and Ethernet 3.0 Live-Online
Analog IC Design, Introduction 3.0 Live-Online
High-Performance Computer Architecture 3.0 Flexible
Wireless Infrastructure: from Antenna Design to 5G, Fundamentals 3.0 Flexible
Digital Logic Design Using Verilog 3.0 Flexible
High Speed Interface Techniques 3.0 Flexible
3. Electives: Back-End
Title units Fall Spring Summer Winter
Introduction to VLSI and ASIC Design 3.0 Live-Online
Comprehensive Signal and Power Integrity for High-Speed Digital Systems 3.0 Live-Online
3D IC Packaging and Physical Verification 3.0 Flexible
Physical Design Flow From Netlist to GDSII 3.0 Live-Online
Practical Design with Xilinx FPGAs 3.0 Flexible
Timing Closure in Silicon IC Design 3.0 Live-Online
Practical Design and Implementation of VLSI Memory Devices 3.0
ASIC Physical Design, Advanced 3.0
High Speed Interface Techniques 3.0 Flexible
4. Completion Review:
Title units Fall Spring Summer Winter
Silicon Chip Design & Semiconductor Engineering Certificate Completion Fee
5. Related Workshops
Title units Fall Spring Summer Winter
Semiconductor Design and Innovation Workshop Series: RISC-V: Understanding Computer Architecture Live-Online
Semiconductor Design and Innovation Workshop Series: High-Precision GHz Op Amp Design
Semiconductor Design and Innovation Workshop Series: Timing Constraint Management for Modern System On Chip

1. Core Course(s): (Choose Three)

VLSI.X410
$990
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-16-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-03-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-10-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-17-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

2 "no meetings" TBA. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Textbooks:

"UVM Testbench Workbook"

"System and Functional Verification Using UVM" 

Note: Both books listed above are required for the course. These books are study guides that contain extensive course notes and step-by-step methodology development practices. Shipment by publisher may take 1-2 weeks.

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X400: Advanced Verification with SystemVerilog OOP Testbench
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Thu, 09-24-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-01-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-08-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-15-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-22-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 10-29-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 11-05-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 11-12-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 11-19-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 12-03-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on November 26, 2026. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Recommended Text:
The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology, Ray Salemi, Boston Light Press, 2013. ISBN-13: 978-0974164939

A Practical Guide to Adopting the Universal Verification Methodology (UVM), Sharon Rosenberg and Kathleen Meade, Cadence Design Systems, 2010. ISBN: 9780578059556

||

Prerequisites / Skills Needed

Prerequisites:

  • VLSI.X400: Advanced Verification with SystemVerilog OOP Testbench
Fall
Summer
VLSI.X400
$980
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Thu, 06-25-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-03-2026 6:30pm 9:30pm Live-Online REMOTE
 

Students may still enroll if they missed the 1st class session. However, they need to communicate with the instructor via Canvas and catch up on all missed work prior to the 2nd class meeting.

6/15/26: Course end date extended by one week. See full schedule for details.

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on 7/16/26.  One additional "no meeting" date TBD. To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: SystemVerilog for Verification, Chris Spear, Springer, ISBN: 9781461407140.  
 

Summer
VLSI.X411
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer
VLSI.X416
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
VLSI.X409
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring

2. Electives: Front-End

EMBD.X415
$820
  • Flexible Attend in person or via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Mon, 09-14-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 09-21-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 09-28-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-05-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-12-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-19-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 10-26-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 11-02-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 11-09-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
Mon, 11-16-2026 6:30pm 9:30pm Flexible SANTA CLARA / REMOTE
 

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: None

Recommended Tools & Materials:
Embedded Systems Architecture: A Comprehensive Guide for Engineers and Programmers, 2nd Edition, Noergaard, Tammy, Newnes, 2012, ISBN: 978-0123821966.

||

Prerequisites / Skills Needed

Skills Needed:

  • Some familiarity with the hardware components of a computer system is required.
Fall
EMBD.X406
$950
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Wed, 09-02-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-09-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-16-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-23-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 09-30-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-07-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-14-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-21-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 10-28-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 11-04-2026 6:30pm 9:30pm Live-Online REMOTE
Wed, 11-18-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on November 11, 2026.  1 "No meeting" date TBA.  To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Recommended Texts:    
PCI-SIG Standards, PCI-SIG (PCI Express). By special arrangement with the PCI-SIG, students will get access to pertinent standards for academic use.     

IEEE 802.3 Standards, IEEE (Ethernet)

 

||

Prerequisites / Skills Needed

Skills Needed:

  • An introductory course or practical experience with operating systems internals, an introduction to computer architecture and organization, and systems programming experience.
Fall
VLSI.X401
$880 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring
VLSI.X415
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
VLSI.X404
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring
VLSI.X405
$820 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring

3. Electives: Back-End

VLSI.X403
$990
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Mon, 09-14-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 09-21-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 09-28-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-12-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-19-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 10-26-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-02-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-09-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-16-2026 6:30pm 9:30pm Live-Online REMOTE
Mon, 11-23-2026 6:30pm 9:30pm Live-Online REMOTE
 

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

No meeting on October 5, 2026. To see all meeting dates, click "Full Schedule" below.

To see all meeting dates, click “Full Schedule” below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials:

A Practical Approach to VLSI System on Chip (SoC) Design, Chakravarthi, Veena S., Springer Nature, 2022,  ISBN: 9783031183638.

||

Prerequisites / Skills Needed

Skills Needed:

  • General understanding of digital logic.
  • Lab exercises require some knowledge of Linux.
Fall
EMBD.X400
$980
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Thu, 07-02-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-09-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-16-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-23-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 07-30-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-06-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-13-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-20-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 08-27-2026 6:30pm 9:30pm Live-Online REMOTE
Thu, 09-03-2026 6:30pm 9:30pm Live-Online REMOTE
 

5/26/26: Course postponed by one week. See full schedule for details.

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Tools & Materials: None

Recommended Tools & Materials:
Advanced Signal Integrity for High-Speed Digital Designs, Stephen H. Hall and Howard L. Heck, John Wiley & Sons, 2011, ISBN: 9781118210680.

Principles of Power Integrity for PDN Design - Simplified, Larry D. Smith and Eric Bogatin, Prentice Hall, 2017, ISBN: 9780132735629.

||

Prerequisites / Skills Needed

Prerequisites:

  • EMBD.X409: Printed Circuit Board Design for Signal Integrity and EMC Compliance
Summer
VLSI.X418
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Winter
VLSI.X408
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer
EMBD.X408
$910 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Summer
VLSI.X414
$980 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring
Currently no classes scheduled. Would you like to be notified when a class is available?
Currently no classes scheduled. Would you like to be notified when a class is available?
VLSI.X405
$820 (Estimated Cost)
Currently no classes scheduled. Would you like to be notified when a class is available?
Spring

4. Completion Review:

O-CE0186
$95
Schedule
 

Please enroll in the VLSI and Semiconductor Engineering Certificate Completion Fee only when all of the certificate requirements have been met and your final grades are posted.

5. Related Workshops

VLSI.800_W2
$95
  • Live-Online Attend via Zoom at scheduled times.
Schedule
Date Start Time End Time Meeting Type Location
Sat, 12-12-2026 9:00am 12:00pm Live-Online REMOTE
 

This course is part of the Fall 2026 Workshop series.

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

To see all meeting dates, click "Full Schedule" below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Fall
Currently no classes scheduled. Would you like to be notified when a class is available?
Currently no classes scheduled. Would you like to be notified when a class is available?

Recommended course sequence

Requisite expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Planning your coursework

Beginners should take introductory courses before advanced. Other courses can be taken based on your interests and professional levels.

Please review course descriptions—Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Related electives

  • Embedded System Hardware Architectures, Introduction (3.0)
  • System Design for Low Power Management (1.0)

Substitutions | Shared credits

You may take one elective outside the certificate curriculum if you receive prior approval from the Academic Services Department.

Some technology courses may be listed in more than one program. However, only one course may be shared between two certificate programs unless otherwise noted.

To receive your certificate

Upon completion of the course sequence, you may request your Semiconductor Engineering Certificate Completion Review.

Requisite knowledge

Technical expertise

You need a degree in a technical field or equivalent knowledge acquired through training and experience in hardware design and development. Experience with UNIX and/or LINUX is required for lab sessions. Knowledge of a programming language such as C, Perl or Bash Shell is helpful.

Please review course descriptions

Make sure you have taken necessary prerequisites or meet the requirements through job experience or previous education before registering for a course.

Grade requirements

Please note that only letter grades of C or higher may be applied to a certificate, and in some programs, students may have more stringent requirements. Students in most employer- and government-sponsored payment programs, such as workforce development, as well as international students on F-1 visas, need to maintain a B average to meet their requirements.

See Grading and Credits Policy for further information.

Program Chair

Certificate Program Advisory Committee

JEFFERY GOODING, MSEE
Account Technology Executive, Cadence Design Systems

SAM HUYNH, Ph.D., MSEE
Principal Member of Technical Staff, AMD
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JIM SCHULTZ, B.S.
Product Marketing Manager, Digital Design Implementation, Synopsys Inc.

MANDAR MUNISHWAR, B.E.
Formal Verification Architect, Intel Data Center and AI Division
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

JOSE RENAU, Ph.D.
Professor, Computer Science and Engineering, Jack Baskin School of Engineering, UC Santa Cruz
Consultant, Esperanto Technologies, Inc.

BENJAMIN TING, M.S.E.E.
Principal Engineer, Micron Technology
Instructor, Silicon Chip Design & Semiconductor Engineering Certificate Program, UCSC Silicon Valley Extension

ARVIND VIDYARTHI, M.S.E.E.
Senior Director, Silicon Design Implementation and Methodology, Altera (an Intel company)|
Program Chair | Instructor, Silicon Chip Design and Semiconductor Engineering

Demo