Silicon Chip Design & Semiconductor Engineering

Students may still enroll if they missed the 1st class session. However, they need to communicate with the instructor via Canvas and catch up on all missed work prior to the 2nd class meeting.

8/27/2025: Change of schedule and instructor. Please review full schedule for details.

Students may enroll until the second meeting.

This class is offered in an online synchronous format. Students are expected to log into this course via Canvas at the start time of scheduled meetings and participate via Zoom, for the duration of each scheduled class meeting.

Electronic Course Materials: You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.

Required Texts: (Click on links to order)

"OOP Testbench Workbook"

"Advanced Verification using SystemVerilog OOP Testbench" 

Note: Both books listed above are required for the course. These books are study guides that contain extensive course notes and step-by-step methodology development practices. Shipment by publisher may take 1-2 weeks.

Short descriptions of weekly homework and partial source code will be distributed in class at no additional expense to enrolled students.

The course is graded by Final Project only - homework assignments are not part of the final grade.

This class meets simultaneously in a classroom and remotely via Zoom. Students are expected to attend and participate in the course, either in-person or remotely, during the days and times that are specified on the course schedule. Students attending remotely are also strongly encouraged to have their cameras on to get the most out of the remote learning experience. Students attending the class in-person are expected to bring a laptop to each class meeting.

To see all meeting dates, click “Full Schedule” below.

You will be granted access in Canvas to your course site and course materials approximately 24 hours prior to the published start date of the course.