This lab-based course covers advanced topics of ASIC front-to-back design automation. At 32nm node and below, ASIC physical designers have to face multi-vdd, multi-vt, high power, noise, and an explosion of process design rules—all while accounting for chip reliability. The course further develops the students' advanced ASIC design skills by introducing state-of-the-art EDA back-end design tools and methodology.
The course provides a 28nm library for students to practice techniques learned in class. After reviewing the design challenges, the course covers UPF-based synthesis and placement. The instructor will give an example of congestion analysis and reduction, and proceed with detailed route analysis and optimization. Students will learn the Clock Tree Synthesis (CTS) and how to optimize timing sign-off in nanometer technology. The course also introduces the hierarchical design flow, power mesh synthesis, and IR drop analysis. The instructor will share tips from extensive professional experience in ASIC implementation over many generations and will also provide basic scripts to facilitate lab exercises.
- Advanced physical design challenges
- DC-topo multi-vt/multi-vdd UPF synthesis
- Power mesh synthesis and optimization
- Placement and IR drop analysis and reduction techniques
- Congestion analysis and reduction
- CTS analysis and optimization
- Detail route analysis and optimization
- Sign-off optimization
- Hierarchical multi-vt/multi-vdd flow
Skills Needed: Basic knowledge of the backend design flow from netlist to GDSII. Knowledge and hands-on experience with Linux/Unix will be required for lab exercises.