VLSI Workshop: Timing Constraint Management

For the Modern System on Chip

Welcome to our immersive Semiconductor Design and Innovation workshop series. During these sessions, you will be introduced to new and established EDA tools that will help you create and manipulate content in new and powerful ways. Each session is led by an industry expert who will guide you through the material and share its real-world implications.

Learning Outcomes

• Describe and discuss timing constraints and why this is critical knowledge as the industry works on the integration of millions of gates onto a single die. for instructors
• Identify use cases where the burden on RTL, Physical Design, and timing engineer can be alleviated through an automated, correct-by-construction approach.
• Demonstrate an ability to properly and effectively use the Timing Constraint Management tool to reduce time-to-market and improve design efficiency

Students are required to bring laptops for class exercises.

This Semiconductor Design and Innovation workshop series is sponsored by the Silicon Chip Design & Semiconductor Engineering at UCSC Silicon Valley Professional Development.