RVfpga: Understanding Computer Architecture

Bring RISC-V to your course in computer architecture using RVfpga

A Hands-On, In-Person, One-Day-Workshop for Teachers

This workshop for people teaching next-generation computer science, electrical, and computer engineering students, will show you how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). You'll be empowered with real-world expertise in computer architecture and the RISC-V instruction set architecture.

Speaker

Sarah L. Harris, Professor of Electrical and Computer Engineering, University of Nevada, Las Vegas. 

What is the RVfpga workshop about?

RISC-V is a rapidly growing worldwide movement of open-source technology to make it easier to target various platforms. We'll look at a commercial RISC-V system targeted to an FPGA, discuss the theory, architecture, and course structure, and show you how to use the hands-on labs that are provided as part of a complete RISC-V FPGA (RVfpga) course.

We'll explore computer architecture fundamentals using Western Digital’s open-source, commercial SweRV EH1 RISC-V core targeted to a Xilinx Artix 7 FPGA on Digilent’s Nexys A7 development board. Everyone will get hands-on experience with this FPGA platform and the software tools.

What will you learn?

• Gain insight into the RISC-V FPGA system and how to get the RISC-V tools up and running
• Learn about the RVfpga labs
• Practice with some of the labs in the workshop
• Understand how to integrate RVfpga into your curriculum.

Topics

• Installing tools (which can be done before the workshop)
• Targeting the SweRV EH1 RISC-V core to an FPGA
• Analyzing and modifying the RISC-V-core and memory hierarchy

This program is co-sponsored by the Semiconductor Engineering program at UCSC Silicon Valley Extension.