ASIC Design using OpenROAD

ASIC Design using OpenROAD

Apr 15, 2023

9:00 a.m. to 1:00 p.m.

3175 Bowers Avenue, Santa Clara, CA 95054

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Cost: Free


Join us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD.  OpenROAD delivers a fast, barrier-free, and low-cost RTL-to-GDS, no-human-in-loop flow for design above 12nm and is one of the tools students can work within UCSC Silicon Valley Extension VLSI Engineering program courses.

Knowing how to use open EDA tools boosts your career prospects in the exponentially growing semiconductor industry!

Free Registration

In this workshop, you’ll:

  • Explore the design space for QoR estimation and implementation.
  • Analyze key design parameters early in the RTL design phase for fast convergence to performance, power, and area targets.
  • Leverage the cloud and other collaborative tools to optimize computational resources for fast run times and efficiency.

Workshop Topics

  • < 24 hrs, No-human-in-loop, RTL to GDS flow in OpenROAD
  • RTL architectural exploration for a good floorplan
  • Timing analysis using OpenSTA
  • Incremental design optimization
  • Verifying your design - DRC and LVS checks
  • Using metrics to track QoR improvements
  • OpenROAD applications

Who should attend?

Students of digital design, verilog design, physical design, and timing closure courses
Experienced professionals working in the VLSI chip design space looking to upskill
Hardware designers looking to innovate at the systems level
Software engineers seeking to learn hardware design and leverage tools for design productivity in a semiconductor design team


  • Matt Liberty, V.P of Engineering, Precision Innovations Inc.
  • Indira Iyer Almeida, Head of User Experience and Outreach, Precision Innovations Inc.

This event is co-sponsored by the UCSC Silicon Valley Extension VLSI Engineering program.