3D IC Packaging and Physical Verification Workshop
Join us for an introduction to the principles, techniques, and applications of three-dimensional integrated circuit (3D IC) packaging—the cutting-edge technology that enables the stacking of multiple integrated circuits (ICs) in a single package. 3D IC packaging offers numerous advantages including performance, power efficiency, and form factor.
You’ll learn about concepts and challenges associated with 3D IC packaging, such as design considerations, fabrication processes, and assembly techniques, and get a chance to work with EDA tools.
- Describe the latest trends and techniques in chip stacking technologies and their purpose in the evolving semiconductor industry.
- Cultivate a mindset of continuous learning and professional growth in 3D IC packaging.
- Demonstrate the use of Synopsys 3D IC in real-world scenarios.
- Lavanya Arya, Ph.D., Principal Engineer at onsemi
Students attending in person need a laptop to participate in lab work.
All are welcome to this free, hybrid event sponsored by the UCSC Silicon Valley Extension VLSI and Semiconductor Engineering program.