Build better chips.
Verify faster. Build better chips.
Semiconductor Design Info Session
Explore the fast-paced world of semiconductor design and verification, and how advanced tools—including AI—are transforming the industry.
At this info session, instructor Mandar Munishwar, a formal verification architect at the Intel Data Center and AI Division, will discuss his SystemVerilog Assertions and Formal Verification course which prepares you to write assertions, create verification test plans, and use simulation and formal tools to catch design issues early and improve first-pass silicon success.
Discover how this hands-on, lab-based course builds practical skills in SystemVerilog, assertion-based verification, and formal verification using industry-standard tools like VCS and VC Formal. You'll better understand emerging trends such as AI-assisted assertion generation and debugging.
See how this course in the UCSC Silicon Valley Extension Semiconductor Design program can help advance your career in chip design and verification engineering.
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- Practical Design with Xilinx FPGAs | June 15
- System and Functional Verification Using UVM | June 18
- SystemVerilog Assertions and Formal Verification | June 22
- Advanced Verification with SystemVerilog OOP Testbench | June 25
- Comprehensive Signal and Power Integrity for High-Speed Digital Systems | June 25