Optimize chip performance with tools for static timing analysis for ASIC, FPGA, GPU, and SoC design.
As transistor technology becomes increasingly complex in the sub-nanometer process, the timing signoff of designs such as ASIC, FPGA, GPU, and SoC becomes more challenging.
In this course, you will learn industry-standard timing methodologies and techniques used during design implementation to achieve targeted clock frequency and ensure manufacturing yield of successful silicon.
The course begins with foundational concepts, including transistor topology, delay modeling through digital gates, and setup and hold characterization. You will gain hands-on exposure to clock constraints, exceptions, and what-if analysis, and learn how to address timing violations in ECO (Engineering Change Order) mode.
Advanced topics include signal integrity (SI) analysis and prevention, process variations, hierarchical and flat analysis, and STA (Static Timing Analysis) margin. The instructor will share practical examples of block-level and full-chip timing closure, budgeting, and debugging skills. Students will also explore EDA tools and practice with small test cases.
By the end of the course, design engineers will be able to perform static timing analysis using PrimeTime, Genus, OpenROAD, or any other STA tool during multiple phases of design implementation.
Linux/Unix skills are required for lab exercises.
