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Timing Closure in IC Design
As integrated circuit designs such as ASIC, FPGA and SoC become increasingly complex, the timing closure of designs becomes more challenging. It involves all stages of physical design, and even RTL changes. The standard industry practice is to perform a Static Timing Analysis (STA) on the design before signing off to manufacturing. Primetime is one of the most popular EDA tools used for this process.
This course begins with the basic timing concepts and STA methodology. It introduces students to setup/hold timing and explains how to fix violations in the design. You will learn what needs to be timed and how to setup a run for STA. The course exposes students to constraints, exceptions and "what if" analysis. It also explains how to address timing violations in ECO mode. Nano-technology topics including noise analysis, prevention and on-chip variations are covered. The instructor shares practical experiences meeting timing closure, budgeting and debugging.
The instructor will provide tool instructions and test cases for practice. Design engineers completing this course will be able to perform Static Timing Analysis using Primetime or any other STA tool in multiple phases of the integrated circuit design process.
- Introduction to Static Timing Analysis (STA)
- Delay and timing analysis
- STA tools and Primetime
- Understanding timing closure
- Understanding exceptions
- Impact of noise in designs
- On-chip variations
- What's fatal for design and what's not
Skills Needed: Linux/Unix skills are required for lab exercises.
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