SystemVerilog Essentials: Functional Verification and Simulation

SystemVerilog enhances Verilog in a number of important areas and is becoming increasingly popular in the field of SoC design and verification. It is the new IEEE standard of 1800. This course covers the essential aspects of SystemVerilog, focusing on functional verification and logic simulation.

This course starts with a brief review of IEEE-1364 Verilog language. Students learn the digital simulation process, including compilation, elaboration/linking, and running simulation. VCS is the main simulator used in the course. However, implementation of NC-Verilog and ModelSim will also be covered. Simulation techniques such as coding style, event ordering, delta cycle debugging, zero width glitch, race conditions, time slices and conditional compilation will be discussed. The course also addresses simulation performance and code coverage.

SystemVerilog essentials include new data types, interfaces, classes, randomization, and overview of assertions. Examples are given to show how these tools help designers with code compaction and system verifications.

This is a lab-based course with hands-on exercises using the simulation tool and process. It provides an opportunity for designers and verification engineers to acquire essential knowledge and experience before progressing to more advanced courses.

Topics include:

  • Review of IEEE-1364 Verilog
  • Simulation techniques and practices
  • Delta Cycles and event ordering
  • Simulation performance
  • SystemVerilog: history and evolution
  • SystemVerilog: new data types
  • Interfaces
  • Classes and randomization
  • Assertions Overview

Skills Needed: Knowledge of basic logic design and familiarity with a high-level programming language (e.g., Perl or C) and experience using Linux environment.

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