Practical DFT Concepts for ASICs: Nanometer Test Enhancements | VLSI.X409
Below 45 nanometers, testing application-specific integrated circuits (ASICs) and system on chips (SOCs) becomes very challenging. The dense spacing of lines on silicon, gigahertz clock rates, newly-emerging fault classes—these factors make it difficult to reach even 98% coverage. This course is ideal for integrated circuit (IC) designers seeking a deeper understanding of test issues, or test engineers wanting to stay current with emerging trends and tools.
This course is filled with engineering insights. It first builds a solid foundation in scan-based design —a necessary skill for understanding more recent techniques like delay-fault testing, scan compression, and built-in self test (BIST). Students will gain hands-on experience in building scan chains and generating test patterns, using Synopsys DFT Compiler (DFTC) and TetraMAX ATPG. You will learn advanced topics such as inserting multiple scan chains, employing sequential ATPG to handle non-scan flops, optimizing DFT logic, understanding LBIST and MBIST, and following nanometer trends in testing.
The systematic hands-on labs reinforce techniques introduced in lecture, and are packed with useful information and practical guidelines. By the conclusion of the course, you will be able to hand off a full-scan design and generate a high-coverage test program for nanometer ASIC.
At the conclusion of the course, you should be able to:
- Use Design for Test Compiler (DFTC) to perform test-smart synthesis and insert scan chains
- Explain in detail how full-scan design enables ATPG to generate a pattern for particular testable fault in fault universe
- Hand off a full-scan design from DFTC to TetraMAX, and make use of all key features of the ATPG tool to generate a high-coverage test program. Employ sequential ATPG to handle non-scan flops
- Explain how on-chip BIST replaces external ATE, generating patterns and compacting the response
- Discuss nanometer trends in testing, such as detecting delay and bridging faults, adaptive scan, strategies for IP cores, testing low-power designs, and supporting testing of on-chip analog content
Skills Needed: A working knowledge of digital logic design is recommended.
Sections Open for Enrollment:
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|Mon, 06-21-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 06-28-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 07-12-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 07-19-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 07-26-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 08-02-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 08-09-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 08-16-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 08-23-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|
|Mon, 08-30-2021||6:30 p.m.||9:30 p.m.||Live-Online||ONLINE|