Course

Embedded Design with Xilinx FPGAs


This hands-on course will introduce you to the world of embedded microprocessor design using field programmable gate arrays (FPGAs). Combining the FPGA fabric with the popular ARM 9 processor cores, it opens up many possible applications with integrated custom peripherals and significant cost/time advantages in design. The course uses the Xilinx Zynq product family including two soft core processors, Picoblaze 6 and Microblaze MCS, and Virtex 7 fabric.

The course begins with an architectural overview of the FPGA family and follows with an in-depth look at the ARM 9 cores. Along the way, you will use the Vivado Design Suite and software development kit (SDK) to develop your code, as well as the cross assembler. The SDK supports both C and C++ compilers with debug facilities. We will use real-world design examples, as well as former students’ projects, to share the creative ideas that this design framework can offer. You will also learn practical approaches to debugging and simply 'bringing the system up'. A project report is required at the end of the course, with an optional student presentation during the final class for extra credit.

Topics include:

  • Introduction to embedded FPGA architecture
  • Introduction to Picoblaze and cross assembler
  • In-class demo of bringing designs 'up' and mapping to Zynq
  • Introduction to Microblaze MCS and Xilinx SDK
  • In-class demo of bringing programs up on the same design framework
  • In-depth look at the ARM 9, AXI, and the fabric interconnections
  • How to build a basic Zynq design in Vivado, using IP and interacting with SDK
  • Additional Zynq based designs with Vivado
  • How to profile designs and debug approaches
  • Optional student project presentations

Note: Students are required to purchase a Zynq-based board for their project (approximately $100, not included in the tuition). Detailed board information and instruction will be provided on the first night of class.

Skills needed: Understanding and experience with basic FPGA design. C or C++ programming experience is required.

Prerequisite(s):


Sections Open for Enrollment:

Open Sections and Schedule
Start / End Date Units Location Cost Instructor
09-04-2019 to 11-20-2019 3.0 CLASSROOM $980

Austin H Lesea

Enroll

Schedule

Date: Start Time: End Time: Meeting Type: Location:
Wed, 09-04-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 09-11-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 09-18-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 09-25-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 10-02-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 10-09-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 10-16-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 10-23-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 11-13-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA
Wed, 11-20-2019 6:30 p.m. 9:30 p.m. Classroom with Online Materials SANTA CLARA

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