Digital Design with FPGA
Field-programmable gate array (FPGA) offers quick-turn, re-configurability, high density, high performance and low non-recurring engineering costs. To meet design requirements, designers must understand the FPGA fabric and how they affect the actual design of the logic functions. This course provides the knowledge and hands-on experience in designing digital logic blocks in FPGA.
The course covers the major FPGA architectures from Xilinx, introduces how to build designs in FPGA and presents specific designs of various digital blocks. Starting from combinational logic, look-up tables, carry chains, and multiplexers, students will learn to design arithmetic and comparator functions using FPGA and test them in action. The instructor then explains sequential flops, fast counters and shift register look-up. The course also explores the various embedded RAM, ROM and finite state machine designs using Xilinx architecture.
The course builds on the knowledge of digital Verilog designs and emphasizes the interaction of FPGA fabric on design without elaborating on FPGA applications. Students gain insight and experience with FPGA design. The course uses Xilinx parts as examples; topics covered are applicable to all major FPGA architectures.
- Introduction to FPGA
- Look-up tables (LUT) and flops on a FPGA fabric
- Building simple circuit and programming on a FPGA board
- Building a digital clock on a FPGA board
- Building combinational logic exploiting LUTs and carry chains
- Building latch and flip-flop
- Fast arithmetic and comparators design
- Single port and dual port RAMS
- Shift register look-up table (SRL)
- Synthesis of RAM and ROM
- FSM design
Note(s): This course requires the purchase of a development board ($150, not included in the course fee) and uses the vendor development kit to implement logic functions. Detailed board information will be provided at the first class meeting.
Skills Needed: Students must have Verilog coding experience to carry out design assignments. FPGA experience is not required.
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