Course

Developing the Nanometer ASIC: From Spec to Silicon


At 32 nanometers and below, today's silicon chips are so complex that few engineers, designers, programmers, and managers fully understand every phase in the IC development cycle. This unique course covers each step in developing an ASIC, explaining in an intuitive and visual manner such key concepts as transistor action, standard cells, RTL synthesis, meeting timing, functional coverage, formal equivalence, physical design, signal integrity, DFT and BIST, tape-out, IC fabrication, and emerging packaging trends.

The course includes hands-on "quick tour" labs to familiarize students with the roles of synthesis, simulation, formal equivalence, and routing tools. The focus is on mostly-digital ASICs with multiple IP cores, low-power goals, and on-chip RF-CMOS /analog blocks. A preview of 22-nm technology - the trigate transistor - is included.

The course is intended for ASIC professionals, both experienced and entry-level who are seeking a more in-depth understanding of the chip development flow. Knowledge gained in this course will improve cross-functional communication with other team members and prepare students for more rigorous study in the ASIC or SoC field.

Topics Include:

  • Overview of ASIC architectures, including networking chips
  • Integration of IP cores: formats, deliverables, watermarks, etc.
  • Overcoming the verification bottleneck: embedded assertions, constrained random tests, equivalence checking and emulation
  • How on-chip firmware code interacts with the chip’s hardware
  • Creating layout for tape-out: metal layers and vias, routing insights, noise avoidance, DFM issues, timing closure
  • How a taped-out design is fabricated onto a silicon die at 32 nm
  • Doing business with silicon foundries: sort, shuttles, corner lots
  • Comprehensive coverage of the chip design flow, from spec through tape-out to fabrication and packaging, equipping students for follow-on courses in RTL design, verification, DFT, and layout

Skills Needed: General understanding of digital logic. Lab exercises require some knowledge of Linux.

Sections Open for Enrollment:

Open Sections and Schedule
Start / End Date Units Location Cost Instructor
09-12-2019 to 10-31-2019 2.0 CLASSROOM $750

Charles T Dancak

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Schedule

Date: Start Time: End Time: Meeting Type: Location:
Thu, 09-12-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 09-19-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 09-26-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 10-03-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 10-10-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 10-17-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 10-24-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA
Thu, 10-31-2019 6:30 p.m. 9:30 p.m. Lab with Online Materials SANTA CLARA

Course Inquiry

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Call (408) 861-3860

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