The course introduces SystemVerilog's basic design building blocks and language constructs, including synthesizable data types and operators, structures and unions, 2-D arrays and loops, and the bus interface unit. Design examples progress in complexity from an easy-to-grasp split counter to a video acquisition subsystem. Students will write their own code, and then synthesize it into 90-nm digital logic for ASICs and FPGAs in the lab. All synthesizable aspects of the IEEE 1800 syntax, especially the versatile bus interface unit, are covered. Eight step-by-step labs highlight proven coding techniques for low-power and high-speed design. The focus of this course is how to write efficient code for logic synthesis. Both ASIC and FPGA tools are provided in our lab but they are not the focus of the course.
- SystemVerilog's basic design building blocks: logic module and bus interface
- How to model logic inside a module, using design-specific "always" constructs
- Custom and built-in data types, and the synthesizable operators that act on them
- Organizing your code and sharing definitions with packages and $unit scope
- Exploiting higher-level constructs: structures, unpacked arrays and void functions
- Coding state machines (FSMs) using custom data types and case qualifiers
- Describing block-to-block interconnections and chip-level busing fabric
- How SystemVerilog resolves classic Verilog pitfalls and annoyances
Skills Needed: Understanding of digital logic concepts, and any programming-language syntax, such as C, VHDL, or Verilog. Hands-on labs use basic Linux commands.