Below 45 nanometers, testing application-specific integrated circuits (ASICs) and system on chips (SOCs) becomes very challenging. The dense spacing of lines on silicon, gigahertz clock rates, newly-emerging fault classes—these factors make it difficult to reach even 98% coverage. This course is ideal for integrated circuit (IC) designers seeking a deeper understanding of test issues, or test engineers wanting to stay current with emerging trends and tools.
This course is filled with engineering insights. It first builds a solid foundation in scan-based design —a necessary skill for understanding more recent techniques like delay-fault testing, scan compression, and built-in self test (BIST). Students will gain hands-on experience in building scan chains and generating test patterns, using Synopsys DFT Compiler (DFTC) and TetraMAX ATPG. You will learn advanced topics such as inserting multiple scan chains, employing sequential ATPG to handle non-scan flops, optimizing DFT logic, understanding LBIST and MBIST, and following nanometer trends in testing.
The systematic hands-on labs reinforce techniques introduced in lecture, and are packed with useful information and practical guidelines. By the conclusion of the course, you will be able to hand off a full-scan design and generate a high-coverage test program for nanometer ASIC.
- Understanding scan-based design
- Generating high-coverage patterns
- How patterns are executed on the ATE
- DFT rules; fixing rule violations
- How to insert and customize scan paths
- Delay defects and other fault models
- Scan compression and reordering
- Built-in self test (MBIST) for memory
- Built-in self test (LBIST) for logic
- Boundary scan for digital and high-speed serial
Skills Needed: A working knowledge of digital logic design is recommended.