Standard logic designs translate automatically and effectively to the world of field programmable logic devices. The course covers common methods based on design constraints used in most design software. You will learn design implementations such as clocking (which creates various clock frequencies from an external reference), including how to handle control and data signals migrating across different clock domains, how to manage clock jitter and debounce input asynchronous signals. You will also learn to manage ground bounce and control power dissipation, while including considerations for safety and security. Practical design examples include discussions of RAM, DSP blocks, basic fabric and A/D converters.
The course places an architectural focus on the Virtex-7, Artix and Kintex families, as well as the Zynq programmable system on a chip. In-class demonstrations and student design projects will feature the Xilinx Vivado Webpack design software. By the end of the course, you should be able to complete practical designs with Xilinx FPGAs and understand design and timing reports. The course includes a student project with design tools; real device implementation or programming is optional.
- Design guidelines and available resources
- How to use the clock manager tools and timing constraints
- How to cross clock boundaries and manage placement constraints
- Two kinds of bounce management: Debounce switches and ground bounce
- How to identify, estimate and control power dissipation
- How to understand and mitigate single error upset effects
- Introduction to security and safety aspects of FPGAs
- Additional constraints
Note: Students are required to purchase a Zynq-based board for their project (approximately $100, not included in the tuition). Detailed board information and instruction will be provided on the first night of class.
Skills Needed: Experience with logic design of digital systems or equivalent knowledge. Familiarity with Verilog design language.