IO Design Fundamentals

This course is an introduction to IO interfacing from one platform to another at both chip and board levels. With today’s chips running over 1GHz, inter-chip communicating is often a limiting factor of the system. Examples of high-speed IO are HDMI, USB 3.0, and 100Base-T.There is no single solution and over the years numerous approaches have been taken, including lowering logic voltages, using differential signals and optical interfaces. The course reviews the various approaches that have been taken in the last two decades, and covers the advantages and disadvantages of TTL, CMOS, low-voltage CMOS, LVDS and optical, from the perspective of speed, power, cost, and complexity.

The course emphasizes fundamental concepts such as transmission line analysis, slew rate, termination, etc. It introduces the basic IO logic, timing analysis and package model, and covers bit error rate, bi-directional IO and decision feedback filters. It does not cover complete circuit designs of the latest IO schemes or board design. Because most solutions are silicon-based, ESD (electro static discharge) concepts and techniques will also be discussed. A circuit simulation tool will be offered to students for exercises but its instruction is not part of the course.

Topics include:

  • Chip interface problems
  • Transmission line analysis
  • Basic IO circuits
  • Various logic families: TTL, CMOS, 3.3 volt CMOS, 1.2 volt CMOS, LVDS
  • High-speed communications
  • Common interface techniques and schemes
  • Timing analysis and package model
  • Electro static discharge (ESD)
  • Optical communications

Skills Needed: A basic course in circuit design and understanding of basic electromagnetic physics.

Prerequisites :

No prerequisites

Sections :

Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X405.(5) 6/18/2019 06:30 PM SANTA CLARA $820 Edison Fong Enroll