The course includes hands-on "quick tour" labs to familiarize students with the roles of synthesis, simulation, formal equivalence, and routing tools. The focus is on mostly-digital ASICs with multiple IP cores, low-power goals, and on-chip RF-CMOS /analog blocks. A preview of 22-nm technology - the trigate transistor - is included.
The course is intended for ASIC professionals, both experienced and entry-level who are seeking a more in-depth understanding of the chip development flow. Knowledge gained in this course will improve cross-functional communication with other team members and prepare students for more rigorous study in the ASIC or SoC field.
- Overview of ASIC architectures, including networking chips
- Integration of IP cores: formats, deliverables, watermarks, etc.
- Overcoming the verification bottleneck: embedded assertions, constrained random tests, equivalence checking and emulation
- How on-chip firmware code interacts with the chip’s hardware
- Creating layout for tape-out: metal layers and vias, routing insights, noise avoidance, DFM issues, timing closure
- How a taped-out design is fabricated onto a silicon die at 32 nm
- Doing business with silicon foundries: sort, shuttles, corner lots
- Comprehensive coverage of the chip design flow, from spec through tape-out to fabrication and packaging, equipping students for follow-on courses in RTL design, verification, DFT, and layout
Skills Needed: General understanding of digital logic. Lab exercises require some knowledge of Linux.