SystemVerilog Assertions and Formal Verification


As more functionality is packed onto denser chips, including system-on-chip (SoC) designs, verification can become a daunting task. Leading design and verification teams are using the power of assertions to manage their verification challenges through both simulation-based and formal property checking verification methodologies.

Prerequisites:


Offering code Offering title
VLSI.X412 SystemVerilog Essentials: Functional Verification and Simulation

Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X411.(2) 7/12/2018 06:30 PM SANTA CLARA 980 Mandar M Munishwar View Enroll

Jitter Essentials


As the world shifts from parallel to serial transmission, timing uncertainty (i.e., jitter) occupies a larger portion of a system's overall timing budget. Effects of jitter, which in the past may have been safely ignored, must be managed today to advance system performance. This course is designed for anyone working with jitter who wants to develop a strong foundation and to clearly understand it.

Prerequisites:


No prerequisites


Comprehensive Signal and Power Integrity for High-Speed Digital Systems


High-speed signaling technologies with multi-gigabit data transfer rates are critical to high-bandwidth communications. However, the physical limitations of the channel (in board, package, and connector), the transceiver circuits, as well as voltage and timing noises introduced along the signal paths, make the design of high-speed links very challenging. Accurate modeling and analysis of high-speed digital systems requires a good understanding of physical effects and system architecture in order to optimize the design parameters in the channel, transmitter, and receiver subsystems.

Prerequisites:


Offering code Offering title
EMBD.X409 Printed Circuit Board Design for Signal Integrity and EMC Compliance
EMBD.X407 Jitter Essentials

Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
EMBD.X400.(2) 7/20/2018 06:30 PM SANTA CLARA 1020 Wendem Beyene View Enroll

Practical Design with Xilinx FPGAs


Field Programmable Gate Arrays (FPGAs) are configurable logic devices with programmable links. They allow you to implement, update, and ship ASICs with low non-recurring engineering costs and are widely used in system design. This course offers a practical introduction to programmable logic design with Xilinx FPGAs, emphasizing design implementation. The course focuses on improving design methods to advance overall design quality; in essence, to bulletproof a design.

Standard logic designs translate automatically and effectively to the world of field programmable logic devices.

Prerequisites:


No prerequisites


Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
EMBD.X408.(2) 6/27/2018 06:30 PM SANTA CLARA 910 Yuchung M Wang View Enroll

SystemVerilog for ASIC and FPGA Design


System-level languages like SystemVerilog are replacing traditional Verilog as the industry standard. Far more than Verilog with a ++ operator, SystemVerilog describes complex logic and bus fabric using concise, yet high-level, constructs.

Prerequisites:


Offering code Offering title
VLSI.X406 Logic Synthesis, Introduction
EMBD.X408 Practical Design with Xilinx FPGAs

Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X413.(2) 7/6/2018 06:30 PM SANTA CLARA 980 Charles T Dancak View Enroll

Practical DFT Concepts for ASICs: Nanometer Test Enhancements


Below 45 nanometers, testing application-specific integrated circuits (ASICs) and system on chips (SOCs) becomes very challenging. The dense spacing of lines on silicon, gigahertz clock rates, newly-emerging fault classes—these factors make it difficult to reach even 98% coverage. This course is ideal for integrated circuit (IC) designers seeking a deeper understanding of test issues, or test engineers wanting to stay current with emerging trends and tools.

This course is filled with engineering insights.

Prerequisites:


No prerequisites


Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X409.(2) 7/2/2018 06:30 PM SANTA CLARA 980 Charles T Dancak View Enroll

Physical Design Flow From Netlist to GDSII


With shrinking process technologies, physical design is becoming extremely challenging. Physical designers are responsible for producing high quality design tapeout, and an understanding of all aspects of physical design from synthesis to tapeout is critical to success. This course is an introduction to the ASIC physical design flow and tools from netlist (gate level) to GDS-II (fractured data).

After an overview of the ASIC physical design flow and synthesis, the course starts with floor planning and block pin assignment.

Prerequisites:


No prerequisites


Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X408.(2) 7/6/2018 06:30 PM SANTA CLARA 980 Sam D Huynh View Enroll

SystemVerilog Essentials: Functional Verification and Simulation


SystemVerilog enhances Verilog in a number of important areas and is becoming increasingly popular in the field of SoC design and verification. It is the new IEEE standard of 1800. This course covers the essential aspects of SystemVerilog, focusing on functional verification and logic simulation.


This course starts with a brief review of IEEE-1364 Verilog language. Students learn the digital simulation process, including compilation, elaboration/linking, and running simulation. VCS is the main simulator used in the course.

Prerequisites:


No prerequisites


Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X412.(3) 9/26/2018 06:30 PM SANTA CLARA 650 Charles T Dancak View Enroll

Advanced Verification with SystemVerilog OOP Testbench


SystemVerilog is the new IEEE-1800 standard combining the hardware description language and hardware verification language. This course focuses on the use of advanced verification features in SystemVerilog. Students will learn the step-by-step processes of creating flexible verification components, which form the basis of modern industry-standard methodologies such as UVM (Universal Verification Methodology). They will also gain experience developing an industrial-strength object-oriented programming (OOP) testbench that is layered, configurable, constrained-random, and coverage-driven.

Prerequisites:


Offering code Offering title
VLSI.X413 SystemVerilog for ASIC and FPGA Design
VLSI.X412 SystemVerilog Essentials: Functional Verification and Simulation

Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X400.(4) 6/21/2018 06:30 PM SANTA CLARA 1020 Benjamin Ting View Enroll
VLSI.X400.(5) 9/18/2018 06:30 PM SANTA CLARA 1020 Benjamin Ting View Enroll

Analog IC Design, Introduction


Today's mobile, wireless, and consumer electronics employ ASICs and high integration SOCs (System on Chip) that often include the analog blocks for signal processing and the associated analog-to-digital interface circuits. Most MEMS, sensors, photovoltaic and electro-optical devices also require analog components. Understanding the basics of analog IC is essential for application engineers as well as circuit and system designers in a wide variety of electronic fields.

Prerequisites:


No prerequisites


Sections :


Section Start Date Time Location Cost Instructor Name Full Schedule Enroll
VLSI.X401.(3) 9/22/2018 08:30 AM SANTA CLARA 880 Min "Adam" Chu View Enroll

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