Course Description:
The Verification Methodology Manual (VMM) for SystemVerilog addresses important aspects of structured verification development for today's chip and system designs. This workshop explores key benefits and other important aspects of structured verification methodology and practices embedded in VMM for SystemVerilog. You will be introduced to the methodology and strategy for building reusable verification components and structured verification environments. Students will preform short exercises by running programs in the lab.
Topics Include:
- Verification planning and goal setting
- High-level structures for building a generic verification environment
- Object-oriented test-bench partitioning, interface definition, and encapsulation
- Code reuse: commonality of objects within a single project or across projects
- Constrained-random stimulus generation
- Coverage-driven verification
- VMM standard library base classes and checker library overview
Prerequisite(s):
This course is for students with practical experience in design verification or for those who have taken introductory courses in SystemVerilog or other design-verification languages. Substantial knowledge of object-oriented programming concepts such as in C++ and Java is required.
Sections:
While there are currently not any sections scheduled for this course, it is offered. To notify us that you are interested in this course and to be informed the next time it is offered, please click "Request Information". We will then ask you to enter or confirm your contact information.
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