Universal Verification Methodology

Electronic design for today's systems and chips frequently requires teams of engineers and millions of dollars of investment. To ensure success, verification engineers build elaborate simulation environments to test the designs before the systems or chips are physically constructed. Silicon Valley is home to the industry leaders in electronic design automation (EDA), who supply software tools for design verification. For years these companies have offered proprietary tools and intellectual properties (IP), and each comes with strengths and weaknesses. The tradeoffs sometimes frustrate users who really want the best of all tools.

Two years in the making, and announced last month, the major EDA and electronic companies have agreed on a single, open standard for verification known as Universal Verification Methodology (UVM). This is a much welcomed advancement for the $200 billion electronic industry. Engineers are embracing the new interoperable standard and companies are poised to achieve increased productivity and cost savings. UCSC Extension is proud to announce an upcoming spring quarter course on this new UVM standard. The course reviews the UVM libraries and utilities that can be used in building complex verification projects with a range of vendor tools. This will be a lab course that includes hands-on practice.

Since our students come with diverse backgrounds and interests, we offer verification courses at several levels in our VLSI Engineering program. Students can progress from Verilog language, design simulation, SystemVerilog for design, assertions, and continue on to verification test bench environments and UVM. We offer our students the most complete and up to date courses for their professional development in this field.