Signal Integrity

The demand for information and the explosion of data require computers and networks to run at higher and higher speed over longer distances. This trend drove the electronic and telecommunication industries to thrive in the last 30-40 years. The digital “bits” that carry the information are increasingly packed in time and space. As a result they begin to corrupt each other. This is known as “Signal Integrity” problem and it is one of the biggest challenges for technical professionals today.

This inevitable trend affects engineering activities at all levels of electronics, from inside the integrated circuits, to chip package, to PCB, to backplane, to system interconnect, over the Internet, and down to devices in consumer’s hands. Signal Integrity is becoming part of the vocabulary for designers and application engineers. Researchers and developers continue to come up with new methods or tools to improve the design process for SI.

Our curriculum has included Signal Integrity (SI) topics for years. We have PCB Design for Signal Integrity and EMC and Jitter Essentials. Our chip timing closure course STA Using PrimeTime includes SI analysis. PLL and Data Recovery Circuits is particularly sensitive to noise. To tie these courses together, we are introducing a comprehensive course this quarter that covers the terminology, models, tools and design methodology, Comprehensive Signal and Power Integrity for High-Speed Digital Systems. Previous students and practicing engineers can learn more topics and take their knowledge to a new level.